Speaker
Description
A new data driven readout architecture for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz’ arbiters thanks to which there is no imposed prioritization and protection against glitches during readout is provided. The system allows not only reading the pixel activity, but also retrieving additional data, both analog and digital, from them. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal so there is no dead time between readouts.
Summary (500 words)
A new data driven readout architecture for highly granular pixel detectors is presented. The area occupied by the arbitration tree and the channel logic is small and allows minimizing the pixel size. A block diagram of the system is shown in Fig. 1. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz’ arbiters, thanks to which the imposed prioritization, known from prior art, was eliminated in favor of arbitration with memory elements. Therefore, a glitch-free protection against switching over to other channels during the readout procedure is gained on one hand, and snapshotting of the states of the channels prior to the arbitration is not needed on the other hand. The system allows not only reading the pixel activity as their addresses, but also retrieving additional data from the them. Novel, yet simple, is in-channel logic, shown in Figs. 2 and 3, that allows dividing the entire readout transaction into multiple phases, with the possibility of dynamically configuring their number. This function is suitable for reading out neighbors in the case of charge sharing. Another advantage of the presented system is the simplification of the entire readout scheme, as it is controlled by only one edge of the clock signal sent into the arbitration tree and the clock’s duty cycle does not necessarily have to be fixed as long as well-known timing dependencies are met. There is no dead time between readouts from different pixels either, as shown on the waveforms in Fig. 4, where a readout from the next requesting pixel follows almost immediately previous one. The both latter features are related to the method of synchronization with the external acquisition system, which takes place almost naturally on the global logic side, so that no distribution of the system clock to each of the channels is required (leading to power savings). Each readout is initiated only during an active level of the clock, and the duration of the inactive level of the clock is the minimum guaranteed time the bus has for settling down new data from the channel. Simultaneously with the change of the clock to the active state, data from the bus are latched in the output periphery and a new acknowledge is generated and distributed. Data latched in the periphery are sent, e.g. serially, to the acquisition system as a bitstream. If there are no channels requesting being read out, a mechanism to keep the synchronization with external system self-activates. Using the pull-ups and pull-downs, an empty data pattern is set on the data bus and is latched in the output periphery in the same way as regular channel data. The described architecture is developed, for reading out multichannel radiation detectors, particularly pixels detectors, where data sparsification is required. It is suitable for new generation of X-ray and charged particles detectors such as the new ITS3/EIC pixel detector. However, it can also be used to read channels one by one in the so-called imaging mode.
