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Description
The ASIC design group at GSI developed an Amplifier With Adaptive Gain Setting (AWAGS) chip. The input stage based on a folded cascode architecture followed by a single-ended to differential conversion and output buffers. In difference to usual designs the capacitive feedback is divided in five capacitances with different values. Starting with the smallest one the capacitances were adaptively added to the feedback depending on the input charge. This concept allows to measure over a high dynamic range (upto 50pC) with the highest precision in the individual gain setting.
The AWAGS ASIC is produced in a MPW run 2020.
Summary (500 words)
The GSI ASIC design group submitted 2020 the Amplifier With Adaptive Gain Setting (AWAGS) ASIC. This amplifier is forseen as the input stage of the at GSI developed analogue transient recorder for the Super-FRS at FAIR. The input amplifier stage is based on a single-ended folded cascode design with an nMOS transistor at the input. The feedback consists of one fixed capacitance of C_0=400fF and 4 additional capacitances (C_1-C_4) which can be optionally added. The maximum feedback capacitance results to 50pF. For discharging the capacitances an active reset is triggered.
The amplifier stage follows the single-ended to differential conversion. Therefore a fully differential miller OTA
is placed. The needed reference voltage is generated by a 10 bit DAC. The used output buffers are able to drive 5pF
capacitive load in parallel to a resistive impedance of 1k Ohm at 1V differential output swing.
As operation mode a manual mode or the adaptive gain setting mode can be configured. In the manual mode the value of the feedback capacitance has to be programmed once before the measurement. Different to the adaptive gain setting mode were the incoming charge determines the gain of the amplifier and ensures the best precision for each charge measurement up to 50pC.
The programming (e.g manual or adaptive mode, set DAC value) and the data readout is done with the serial interface on chip. In case of the adaptive gain setting mode is selected the information of the active capacitances in the feedback can be read out via the interface.
The preliminary characterization at room temperature of a readout channel get a noise value of 0.3fC and a maximum
input charge of over 50pC. Therefore a dynamic range of more than 150000 results. The measured linearity is better
than 0.5% over the full dynamic range. For the manual gain setting the stable output voltage is reached after 30ns for
a max. amplitude of 1V. In case of using the adaptive gain setting mode the stable output values are present after
max. 140ns if all feedback capacitances are added.
The ASIC is produced in an UMC 180nm CMOS process on an MPW run middle of 2020 and arrived in April 2021 at GSI.
The final results of the characterization will be presented in this contribution.
