Speaker
Description
With the ever-increasing amount of data from HEP experiments, the transmission rates must keep up. To mitigate the exponential growth of the total loss due to the increased frequency, the 4-Level Pulse-amplitude Modulation (PAM-4) could be envisaged, allowing to reach 56 Gbps or even 112 Gbps in extremely high-end applications. A system using PAM-4 encoders and transceivers has been built based on FPGA as a proof-of-concept to demonstrate potential future links. In this talk, the PAM-4 modulation will be introduced, the performance of this initial system will be presented and the challenges for future links will be discussed.
Summary (500 words)
With the ever-increasing amount of data produced by the High Energy Physics experiments, the transmission rates from the detectors to the back-end stages must keep up. To mitigate the exponential growth of the total loss due to the increased frequency, the 4-Level Pulse-amplitude Modulation (PAM-4) could be envisaged. Where the line rate of Non-Return to Zero (NRZ) modulated signals is capping at 28 Gbps per lane, PAM-4 allows to reach 56 Gbps or even 112 Gbps in extremely high-end applications. Investigating the implementation of such links in FPGA is one of the activities carried out by the Work Package 6 of the CERN EP Research and Development programme. In this framework, a proof-of-concept system of high-speed links using NRZ-28 Gbps and PAM4-56 Gbps has been built, based on a Xilinx Virtex evaluation platform and various commercial optoelectronics transceivers. 53.1 Gbps PAM-4 and 26.6 Gbps NRZ eye pattern have been analysed using high-end oscilloscopes and optimized using various equalization schemes. PAM-4 standard Forward Error Correction (FEC) codes have also been implemented and characterized over electrical and optical layers in terms of coding gain and latency. Finally, the telecom and datacom markets were investigated to identify development perspectives for the research and development for future links.
In this talk, the PAM-4 modulation scheme will be introduced, the performance of the proof-of-concept implementing these high-speed links will be presented and the current and future challenges for an error-free communication will be discussed.
