Speaker
Description
The CMS detector will undergo a major upgrade for Phase-2 of the LHC program: the HiLumi LHC. The Phase-2 CMS back-end electronics will be based on the ATCA standard, with node boards receiving the detector data from the front-ends via custom,
radiation-tolerant, optical links. An ATCA hub board, the DAQ and Timing Hub, will provide the interface between the back-end nodes and the central Trigger, Timing, and DAQ systems. This paper presents the progress on the development towards the DTH design. Measurements are presented showing the performance achieved for all main DTH tasks: clock distribution, DAQ throughput, and hub-to-node networking.
Summary (500 words)
The upgraded CMS detector will be read out at an unprecedented data rate of up to 60 Tb/s with an event rate of 750 kHz, selected by the level-1 hardware trigger, and an average event size reaching 10 MB. The back-end electronics will be based on the ATCA standard, with
node boards receiving the detector data via optical links from the front-end electronics and processing them.
Back-end electronics will be connected to the central Trigger, Timing, and DAQ systems, as well as the CMS control network, by a duo of custom boards: the DAQ and Timing Hub (DTH), and an additional DAQ800 node board. The DTH will connect to all back-end boards and be responsible for the distribution of clock, trigger, and fast-control commands from the central trigger control system to all back-end electronics, and the handling of throttling signals in the opposite
direction. The DAQ interface for the event data uses point-to-point optical links connecting back-end boards to the DTH using a custom lossless `SLinkRocket' protocol. The event data are aggregated in the DTH and transmitted via standard 4x100 Gb/s Ethernet links to event
building computer nodes at the surface. Where detector needs exceed 400 Gb/s in a single ATCA crate, additional DAQ800 boards can be used to augment the DAQ throughput.
The introduction of timing detectors for Phase-2 CMS, aiming for a 30 ps precision on individual detector hits, strongly tightens the requirements on the clock and timing information distributed
throughout the experiment, with different sub-detectors introducing different requirements.
The R\&D process towards the DTH design spans three prototyping branches: one for the clock distribution, one for the event building and DAQ throughput, and one for the managed Ethernet switch connecting the back-end boards to the control network. At past TWEPP events we
have presented the design of the first DTH prototype, and discussed some of the design challenges encountered. The current paper summarises the progress made in the three prototype branches, and how these branches now converge into the final prototype: the DTH-P2. Performance measurements are presented of all three main DTH tasks, showing that most of the CMS Phase-2 can be met already with these prototypes. The quality and stability of the distributed clock will be quantified, the DAQ throughput and buffering performance will
be presented, and the back-end Ethernet connectivity demonstrated.
We will conclude with a brief look forward to the qualification of the final DTH and DAQ800 designs.
