Speakers
Description
Chip design, is a lengthy process, which comes with high development efforts and costs and is a crucial milestone for the overall success of the project. Readout electronics for particle detectors resemble each other to a high degree, thus developing a software-adaptable receiver chain covering a large range of application scenarios is an attractive concept. With a generic approach, designed independently, these risks are shifted to project-independent stages, which substantially reduces development time and costs, enabling also smaller projects and rapid prototyping.
A generic receiver low power system-on-chip is conceptualized. The central block is a software-scalable, high-performance ADC combined with a configurable front-end with adjustable impedance. Succeeded by an SRAM memory as a buffer and a digital signal pre-processing system. The high integration degree and complexity of the system is accompanied by an advanced 28nm CMOS technology, mitigating the area overhead of a generic approach and enabling high-speed electronics at an acceptable power consumption. Common approaches in detector readout use blocks like TDCs for the extraction of information from detector signals. While simpler and inherently efficient, they reduce the options for direct reusability in various application areas and require a repeated design effort. In this novel approach, the sampled waveforms enable sophisticated signal processing, leveraging the potential of a complex system-on-chip in a modern technology. This will enable an increased resolution for time and energy measurements, as demonstrated by (Jokhovets, 2019). Such methods enable a timing resolution below 100ps from sampling at nanosecond intervals. Furthermore, it will allow a pre-clustering and data reduction on chip, reducing the transmission bandwidth and amount of necessary post-processing hardware. An integrated 16kByte SRAM buffer will allow for local data buffering and reduction of transmission speed, adjustable to the expected hit rates.
For these developments, an in depth study of existing readout solutions was performed, whose results are summarized in this contribution. Additionally, it will give an introduction in the algorithm development process and the developed Simulink framework.
Another focus of this contribution is the software-scalable ADC that consists of similar ADC cores. They can be arranged in different ways to adjust to different specifications. For the core ADC, successive approximation register (SAR) ADCs are implemented as their mostly digital nature scales well with technology, leading to higher performance and decreased chip area. The ADCs can be concatenated which increases the resolution without penalties in sample rate. For the first engineering sample, a high-precision mode with 12 bit resolution and a medium-precision mode with 9 bit is foreseen. The maximum sample rate is 500 MS/s with no bound for the lowest sample rate. For higher rates, the ADCs can also be multiplexed in time (time-interleaving). Using two time-interleaved ADCs for the first prototype, a maximum sample rate of 1 GS/s can be achieved. It is also investigated to use both time-interleaved ADCs independently to read out two channels, gaining flexibility for multichannel designs. The silicon area for the ADC pair is conservatively estimated to 0.24 mm2 , allowing an upscaling of the number of channels in future developments.
Summary (500 words)
A software-adaptable receiver tackles some of the highest challenges in particle detector development. With a generic approach it reach the same performance as a dedicated development, it covers most application fields and can cut down development times and costs. Prototyping and verification of readout methods prior to the building of the complete systems are also facilitated. An in-depth study of existing particle detectors was conducted to define requirements that such a system will have to fulfil. In parallel, a first investigation of configurability is conducted to assess feasibility using an ADC as the central block in the receiver.
