Speaker
Description
The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65nm ISC process in the framework of the CERN-EP R\&D on monolithic sensors and the ALICE ITS3 upgrade.
It features a 32x32 binary pixel matrix at 15 $\mu m$ pitch with event-driven readout, based on GHz range time-encoded digital signals including Time-Over-Threshold.
The chip proved fully functional and efficient in test beam allowing early verification of the complete sensor to readout chain.
The focus is on the design and in particular the digital readout and its perspectives with some supporting results.
Summary (500 words)
Monolithic Active Pixel Sensors (MAPS) combine readout and sensor circuitry onto the same die, allowing fabrication in standard CMOS processes, making them interesting for different applications including detectors for particle physics experiments, thanks to the high circuit density and radiation tolerance of deep sub-micron nodes.
The TowerJazz Panasonic Semiconductor Company (TPSCo) 65nm ISC imaging process is being investigated as a potential candidate for future vertex detectors in the context of the CERN-EP R\&D on monolithic sensors and the ALICE ITS3 upgrade project \cite{akluge} \cite{mmager}.
This contribution will target the design aspects of the Digital Pixel Test Structure (DPTS), a 1.5x1.5 $mm^2$, 32x32 pixels MAPS prototype. This chip was designed to explore the TPSCo 65nm ISC process.
The readout system is fully asynchronous and event-driven, which makes it an unconventional alternative to strobed architectures. Hit position and Time-Over-Threshold (ToT) are encoded in time over a binary sequence that is streamed off-chip by means of a single differential CML output. The encoding circuit is distributed and independent over a single 32 pixels column. Each column consists of digital delay lines geometrically arranged to generate variable pulse lengths that reflect the position of the hit in the column and the position of the column in the matrix itself, completing the hit coordinates in a set of two pulses. Encoding of ToT, on the other end, is achieved by re-transmitting the same sequence after a ToT interval.
Each pixel packs a sensor optimized for charge collection, an amplifier discriminator front-end and a section of the distributed readout. The chip can be configured by means of a simple serial interface and allows for single pixel masking and electrical pulsing by tunable charge injection on the input electrode.
Moreover, a single monitor pixel is present in the matrix with dedicated analog output for a detailed testing of the front-end circuitry. The DPTS allowed early verification of the novel sensor geometry, front-end and key aspects of the TPSCo 65nm ISC process by proving fully functional and efficient in test beam.
The performance, limits and challenges of the architecture will be addressed in this contribution with a point to scalability to large stitched sensitive areas with as an example how it was modified for more robustness in the stitched sensor prototype MOST.
