13th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors (HSTD13), Vancouver, Canada

A 28Gbps PAM4 VCSEL Driving ASIC for the Front-end Readout Application in High-Energy Physics Experiments

Not scheduled

20m

Conference room (Wosk Centre)

Poster ASICs

Speakers

Juncheng Li (Central China Normal University)Prof. Di Guo (Central China Normal University)

Description

Optical communication has been widely used in high energy physics experiments. 4-level pulse amplitude modulation (PAM4) technology is becoming the potential solution for higher rate optical data transmission with its advantages of more efficient fiber utilization and lower analog bandwidth requirement at the same data rate. This paper presents the design and test results of a 28Gbps PAM4 vertical cavity surface emitting laser (VCSEL) driving ASIC fabricated in 55nm CMOS process. A novel output driver stage is proposed with a 2:1 cross-combination PAM4 transform topology and a dual-feedforward capacitor structure to improve eye-diagram quality.
The 28Gbps PAM4 VCSEL driving ASIC consists of a Least Significant Bit (LSB) channel, a Most Significant Bit (MSB) channel, a novel PAM4 output driver circuit and the corresponding bias circuits. The LSB/MSB channel consists of an input equalization stage and a pre-amplification stage with shared-inductor peaking and active feedback technologies. The proposed novel output driver circuit adopts a simplified cross-combination topology to convert two independent non-return-to-zero (NRZ) voltage data directly into PAM4 current data and drive the VCSEL. On-chip AC coupling and stacked current mirror structures are used to match the threshold voltage of the VCSEL (about 1.8V), and a dual-feedforward capacitor structure, working together with the stacked current mirror, is proposed to effectively improve the bandwidth and the eye-diagram quality.
The core area of the 28 Gbps PAM4 VCSEL driving ASIC is 0.55mm×1.5mm. The simulation results show that the core power consumption of the ASIC is 133.8mW, the open and clear PAM4 eye-diagram can be obtained at the rate of 28Gbps, the ratio level mismatch (RLM) is better than 0.95, and the amplitude is 9mA. The chip has been taped out and will be tested in September, the test results, including electrical and optical tests, will be presented and discussed in the meeting.