Sep 26 – 30, 2011
Vienna, Austria
Europe/Zurich timezone

Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

Sep 29, 2011, 4:00 PM
2h 30m
Vienna, Austria

Vienna, Austria

<font face="Verdana" size="2"><b>Vienna University of Technology</b> Department of Electrical Engineering Gusshausstraße 27-29 1040 Vienna, Austria
Poster ASICs Posters

Speaker

Tiankuan Liu (Southern Methodist University (US))

Description

The upgrade of ATLAS Liquid Argon (LAr) calorimeter readout calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. We are addressing the problem by iterative design previously reported at TWEPP with a commercial 0.25 μm silicon-on-sapphire CMOS technology we have evaluated to be radiation tolerant. In this paper, we present the updates for the design and post layout simulation of a two lane serializer array with each lane runs at 8 Gbps, and a total of 16 Gbps aggregated data rate. A newer process in the same SOS technology has been announced by the foundry for which new simulation results will be presented.

Summary 500 words

The upgrade of ATLAS Liquid Argon (LAr) calorimeter readout calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. The SMU group has been working on a serializer ASIC for this optical link system, and has reported in TWEPP 2010 the measurement results (both in lab and with irradiation of a 200 MeV proton beam) of a prototype we call LOCs1, which is a 5 GHz 16:1 serializer, and a 5 GHz LC-PLL. Both designs are based on a commercial 0.25 μm silicon-on-sapphire CMOS technology. In this paper, we present the updates for the design and post layout simulation of a two lane serializer array with each lane runs at 8 Gbps, and a total of 16 Gbps aggregated data rate. The two 16:1 serializers share one LC-PLL to save power. Detailed design techniques will be presented and discussed for this novel radiation tolerant high speed serializer array, including some system level issues such as the effect of signal equalization in the receiving end of a nonlinear or a linear optical link system. This ASIC design is still based on the above mentioned SOS technology, with a particular process (the GC process) that we have evaluated to be radiation tolerant. A newer process in the same SOS technology has been announced by the foundry. We will also present the simulation results with this process and compare the gain in speed and power.

Primary author

Dr Luis Hervas (CERN)

Presentation materials