Einstein Telescope is the future European Laboratory for gravitational waves. The discovery of gravitational waves (GW), in 2015, 100 years after the publication of Einstein’s general theory of relativity, was soon followed, in 2017, by the assignment of the Nobel prize for physics to three scientists of the LIGO-VIRGO collaboration. LIGO in the USA and VIRGO in Italy are, at present, the...
Sardinia has an age old history told by a great cultural heritage and the nuraghi are probably the most important archaeological and cultural evidence. These majestic stone towers, built in the second millennium B.C., have represented a long term landscape marker and a symbolic reference point for Sardinian communities. Extraordinary ancient architects designed and built at least 7000...
A novel Data Acquisition (DAQ) system, known as Level-1 Data Scouting (L1DS), is being introduced as part of the Level-1 (L1) trigger of the CMS experiment. The L1DS system will receive the L1 intermediate primitives from the CMS Phase-2 L1 trigger on the DAQ-800 custom boards, designed for the Phase-2 central DAQ. Firmware is being developed for this purpose on the Xilinx VCU128 board, with...
H2GCROC is the 130nm CMOS ASIC designed to read out the SiPMs coupled to the scintillating tiles of the back hadronic sections of CMS HGCAL (High Granularity Calorimeter). Each of its 72 channels is composed of a current conveyor, a high-gain preamplifier, a shaper, and ADC to read the energy, with two discriminators connected to TDCs for time-of-arrival and time-over-threshold information,...
With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65nm CMOS, are radiation tolerant (200 Mrad) with low power consumption (<2.5...
The RHIC interaction rate at sPHENIX reaches around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200. Critical measurements often require the analysis of particles produced at low momentum. This prohibits adopting the traditional approach, where data rates are reduced through triggering on rare high momentum probes. We propose a new approach...
This talk describes the characterisation and validation campaign of the prototype of the CMS Readout Chip (CROC), a 65 nm CMOS pixel readout ASIC for the CMS Inner Tracker upgrade for High Luminosity LHC. This validation campaign includes tests with single-chip and multi-chip modules, irradiation campaigns, test beams and wafer-level tests. The main results obtained in the testing of the CROC...
The RD53 Collaboration, established in 2013 as a joint effort between ATLAS and CMS pixel ASIC communities on 65nm CMOS technology, is now in the phase of implementing final pixel readout chips, referred to as RD53C revisions, that will be used into upgraded pixel detectors at HL-LHC. The purpose of this work is to provide a comprehensive review of most important architectural design choices,...
We present the deployment and testing of an autoencoder trained for unbiased detection of new physics signatures in the CMS Global Trigger test crate during LHC Run 3. The GT test crate is a copy of the main GT system, receiving the same input data, but whose output is not used to trigger the readout of CMS, providing a platform for thorough testing of new trigger algorithms on live data, but...
The COLUTA ASIC is an 8-channel 15-bit 40 MSPS ADC fabricated in 65 nm CMOS for the upgrade of the readout of the ATLAS LAr calorimeter for the high luminosity LHC. The ADC architecture couples a 3.5-bit Multiplying-DAC (MDAC) stage to a successive approximation register (SAR) ADC with a digital back-end that outputs sample data continuously via 640 Mbps serial LVDS. The analog performance and...
The baseline architecture for the ATLAS Phase-II upgrade has a single-level hardware trigger (Level-0 Trigger) with a maximum rate of 1 MHz and 10 μs latency. A full-function Global Common Module (GCM) prototype has been designed and implemented for the core part of the Level-0 Trigger, the Global Trigger. This GCM features two of the latest Adaptive Compute Acceleration Platform (ACAP)...
The LHC upgrade requires redoing the LAr calibration system which should provide a 16-bit range signal with 1‰ accuracy while being radiation tolerant. The former operating principle is used: a precise current is stored in an inductor, when it is switched off, a pulse is generated to be injected in the readout electronics. This is achieved by two chips: the first one, in TSMC 130nm, provides...
FLX-182 is a PCIe card designed for the readout system of the ATLAS experiment for the High Luminosity phase of LHC starting in 2029. FLX-182 is responsible for decoding and transferring data from the front-ends into the host server memory, and receiving and distributing timing, trigger and control information. About six hundred FLX-182 will sustain 4.6 TB/s of total throughput at 1 MHz data...
The MOSS (Monolithic Stitched Sensor) chip is a
monolithic pixel prototype chip measuring (\qty{25.9}{cm}\times\qty{1.4
}{cm}). It was designed to explore the stitching technique,
to investigate the achievable yield and as a proof of concepts for
the sensors for the ALICE ITS3 upgrade. It was manufactured in
early 2023.
This submission will focus on the MOSS chip and on its...
As part of the CMS Phase-2 upgrade, a prototype of the receiver of raw trigger data from the HGCAL endcap has been implemented using the Serenity ATCA platform. The receiver firmware was developed to test the unpacking of data from the front-end endcap trigger concentrator ASIC and measure its performance and stability. The firmware mainly consisted of unpacker blocks to decode ASIC packets,...
During the next LHC Long Shutdown, the innermost three layers of the ALICE Inner Tracking System will be replaced by a new vertex detector composed of curved ultra-thin monolithic silicon sensors. The R&D initiative on monolithic sensors of the CERN Experimental Physics Department, in synergy with ALICE ITS3 upgrade project, prepared the first submission of chip designs in the TPSCo 65 nm...
Several physics experiments are moving towards new acquisition models. In this work implementation of Remote Direct Memory Access (RDMA) directly on the front-end electronics has been explored, in this way is possible to free part of the computing farm's CPU resources. The work also introduces new verification techniques for verifying RDMA over Converged Ethernet (RoCE) firmware block...
ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC)2 shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution for small signals. ALFE2 is characterized using a Front-End Test Board (FETB) based on a...
The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications.
This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the...
4D tracking with ~10ps timing is crucial for reducing the combinatorial challenge of track reconstruction at high pileup densities, it offers completely new handles to detect and trigger on LLP and enables particle-ID capabilities at low transverse momentum. At the Muon Collider, the timing information will be essential for reduction of BIB. A high-precision TDC is a critical block necessary...
ALTIROC3 is the second version of the ASIC for the ATLAS High Granularity Timing Detector to read out full size LGAD sensors (15x15 pixels of 1.3mm x 1.3mm). The ASIC, designed in 130nm technology, comprises around 250k flip-flops, more than 1000 8-bit configuration registers, and several clock domains and implements different analog IP-blocks critical for digital data acquisition and...
The ALICE collaboration is developing the new Inner Tracker System 3 (ITS3), a novel detector that exploits the stitching technique to construct single-die monolithic pixel sensors of up-to 266 mm x 93 mm. ITS3 requires all hits from a particle flux of 4.4 MHz/cm2 to be transmitted on-chip to one of the sensor edges. This on-chip readout is limited by a power budget of 20 mW/cm2, a readout...
The IGNITE project is developing solutions for the next generation of trackers at colliders. It plans to implement an integrated system module, comprising sensor, electronics, and fast readout, aimed at 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In the present paper we present recent advancements on the design of a prototype ASIC,...
This work is concerned with the design and the characterization of front-end channels, developed in a 28 nm CMOS technology, conceived for the readout of pixel sensors in future, high-rate applications at the next generation of large particle accelerators.
Two front-end architectures are discussed. In the first one, an in-pixel flash ADC is exploited for the digitization of the signal,...
The Level-1 trigger scouting system of the CMS experiment aims at intercepting intermediate data produced by the L1 trigger processors, before the final trigger decision.
This system can be complemented by adding the raw stream of data collected from the detector front-end, where the throughput is manageable. An implementation of the triggerless readout is realized by reading a sector of the...
We present first results obtained with a prototype 4D-tracking demonstrator, using sensors and electronics developed within the TimeSPOT project, and tested on a positive charged pion beam at CERN SPS. The setup consists of six small tracking layers in a row, having area of about 3 mm squared each, three of which equipped with 3D-trench silicon sensors and three with 3D-column diamond sensors....
We present details on the new Level-1 Global Trigger at CMS for the upcoming high-luminosity operation of the LHC. Our focus is on the newly developed firmware, which employs a bottom-up generic approach to enhance menu adaptability and accommodate the increase in upstream information. We also highlight our efficient pipelining strategy that ensures excellent routability at 480 MHz....
High-speed multichannel ADCs are costly and require complex FPGA firmware to communicate with them. The Multi-Voltage Thresholding (MVT) approach can replace to some extent an external ADC with internal resources of an FPGA, thus reducing costs and complexity. The MVT approach needs only a few low-cost external components. The focus of the talk is presenting an open-source IP-Core that...
A new application for monolithic pixel detectors is NASA’s AMEGO-X project [1], which is a low-orbit gamma ray observatory for multimessenger astrophysics, proposed as a 3 to 5 year mission. For the 40-layer gamma-ray telescope, which will consist of over 64000 sensors with a total area of more
than 25 m², a new low power < 2 mW/cm2 and high dynamic range 20 – 600 keV monolithic active pixel...
A full characterization of the BigRock high-speed, low-power analog front end (AFE) will be presented. The BigRock AFE previously described in [1] has been refined in a second generation testbed ASIC, Pebbles. The AFE utilizes a current-mode signal path that has been designed for 4D tracking applications with precision time resolution of order 50 ps. The preamplifier concept is based on a...
In preparation for the High-Luminosity era of the LHC, the CMS experiment will replace the existing calorimeter endcaps with a novel device - the High Granularity Calorimeter (HGCAL), having around six million readout channels. The electronics system for this upgrade project is highly specialised and complex, involving multiple layers of data transfer, so testing must be carefully planned. The...
The development of the CMS Barrel Calorimeter Processor (BCP) for the high-luminosity LHC poses a challenge due to strict power requirements. To minimize the risk of performance degradations or component damage, a project-specific and inexpensive evaluation board has been designed with multiple DC power circuits to safely test and evaluate them outside of the expensive BCP. The planned tests...
University of Bergen is involved in developing two calorimeters: (1) the pixel section of the Electromagnetic Forward Calorimeter (FoCal-E) for the ALICE Upgrade and (2) the Digital Tracking Calorimeter (DTC) for the proton Computed Tomography (pCT) prototype. Both designs utilize the ALPIDE sensors which are connected to aluminum-polyimide flexible cables applying Single-point Tape Automated...
The paper describes a new figure of merit reachable in term of very low power dissipation for a 12 bit, 40MS/s Analog to Digital Converter in a CMOS 65nm process with 1V power supply. A differential time interleaved successive approximations register architecture is used. Each individual ADC channel is optimized regarding power consumption hence parallelizing 28 ADC channels in an analog...
The Belle II collaboration has initiated a program to upgrade its detector in order to address the challenges set by the increase of the SuperKEKB collider luminosity, targeting 6x1035 cm²s-1. A monolithic CMOS pixel sensor named OBELIX (Optimized BELLe II pIXel) is proposed to equip 5 detection layers upgrading the current vertex detector. Based on the existing TJ-Monopix2, OBELIX is...
We present the architectural design, prototype fabrication and and first results for the High Pitch digitizer System-on-Chip (HPSoC). The HPSoC is a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip is being fabricated in 65nm technology and targets the following features:...
We present the development of a data acquisition system dedicated to de-
tectors using the Timepix4 ASIC, developed in 65nm CMOS technology by the
Medipix4 Collaboration, as integrated front-end.
A control board is needed for system configuration and data acquisition,
up to the maximum bandwidth of 160 Gbps. To avoid the need for multiple
custom boards, we designed a system based on...
Upcoming upgrade of the ALICE Inner Tracking System (ITS3) foresees the use of wafer-scale MAPs bent into a cylindrical shape. Test beams employing the current ALICE Alpide chips, bent to foreseen ITS3 radii, showed that MAPs remain fully functional. However, some electrical effects, like (PS) power supply current changes and voltage shifts, were observed. The results suggest that these are...
This paper introduces a prototype of a GaN FET based 200 W DC-DC converter. Its design has been carried out to ensure optimal efficiency and minimal electromagnetic interference (EMI) issues that are commonly associated with the high switching frequency converters. To achieve this, hardware-in-the-loop (HIL) techniques have been used to enhance the control at high switching speed, and ANSYS...
The High Granularity Timing Detector (HGTD) is an ATLAS Phase II upgrade project, the goal of which is to provide accurate time measurements for tracks to mitigate pile-up effect. DC/DC converters, BPOL12V, are implemented in the Peripheral Electronic Boards (PEB) and used to generate voltages for a bunch of ASICs. Due to the working environment constraints of HGTD, the BPOL12V will be...
Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are constantly challenged. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which...
In this poster we present our approach to design power supplies that are resilient to magnetic field that can reach up to 1 T, we will illustrate the engineering challenge to have a power supply that can safely operate in radiation and magnetic fields. We will summarize the test we have performed starting from basic components like inductors, then sub-parts and complete modules. We will...
FPGA prototyping enables hardware acceleration for ASIC verification. Cadence Protium, an FPGA based platform, enables ASIC designers to prototype their RTL code in an easy and automatically way. As the RTL codes stay untouched during the process, the Protium provides a reliable model of the ASIC for early developments of DAQ and control systems. Protium advanced Blackbox flow allows in...
The High-Luminosity phase of the CERN Large Hadron Collider will pose new challenges for the detectors. The Electromagnetic Calorimeter (ECAL) of the CMS experiment will be equipped with a completely new readout electronics to cope with increase in the number of pp collisions per bunch crossing, as high as 200, and higher noise induced by radiation. Two on-beam vertical integration tests were...
RDMA communication is an efficient choice for many applications, such as data acquisition systems, data center networking and any other networking application where high bandwidth and low latency are necessary. RDMA can be implemented using a large array of options which need to be tailored to the needed use case in order to get optimal results. Aspects such as the effects of using multiple...
A new Forward Calorimeter (FoCal) system has been proposed as part of the ALICE upgrades planned for LHC Run 4 which features a Si+W electromagnetic calorimeter. A first tower prototype corresponding to 1/5 of the nominal module of the electromagnetic calorimeter has been built in 2022. It is composed of 20 passive layers of tungsten absorber interleaved with 18 active layers of...
A new silicon tracker detector (ITS3) will be installed in ALICE Inner Tracking System during the LHC long shutdown 3. We develop a 10.24Gbps Data Serializer and Wireline Transmitter (GWT-PSI) circuit for the readout of the detector. A 16-to-1 multiplexer architecture achieves low power consumption (28mW) and avoids high-frequency (> 640MHz) clock signals in the circuit. A clock-cleaning PLL...
Results are presented for gamma and neutron irradiation tests for SFP+ transceivers. The radiation tolerance of the electronics components used in the detector area is a key of the electronics systems at high energy physics experiments. We tested four types of SFP+ transceivers from Ficer. Gamma rays were irradiated up to O(100) Gy at the Cobalt-60 facility of Nagoya University. Neutrons were...
This contribution presents results from the RD50-MPW family of monolithic High Voltage CMOS (HV-CMOS) pixel chips, which are developed by the CERN-RD50 collaboration to study this technology in view of the harsh requirements imposed by future hadron colliders on tracking systems. Parameters especially considered in this programme are radiation tolerance, time resolution and granularity. This...
The extremely low dark current of silicon carbide (SiC) detectors, even after high-fluence irradiation, is utilized to develop a beam monitoring system for a wide range of particle range, i.e., from the kHz to the GHz regime. The system is completely built from off-the-shelve components and is focused on compactness and simple deployment. Beam tests on a 50 um thick SiC detector reveal, that...
This paper addresses the challenge of mitigating the effects of radiation on the electronic systems of the Large Hadron Collider (LHC) by introducing BatMon, a battery-powered, MCU-based wireless radiation monitoring system. The paper proposes software mitigation schemes that can be used alongside an external watchdog to guarantee higher availability of the application without impacting the...
The MDT Trigger Processor (MDTTP) is a key ATLAS Level-0 Muon trigger upgrade component designed to meet High-Luminosity LHC requirements. The MDTTP will use MDT hits in the trigger for the first in ATLAS to improve the momentum resolution of muon candidates provided by RPC and TGC detectors and reduce fake muon trigger rate.
The MDTTP hardware is based on the Apollo ATCA platform. The...
For the High-Luminosity Large Hadron Collider era, the trigger and data acquisition system of the Compact Muon Solenoid experiment will be entirely replaced. Novel design choices have been explored, including ATCA platforms with SoC controllers and newly available interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger data analysis will be performed through...
The ATLAS collaboration will replace its inner detector by an all-silicon tracker (ITk) for the HL-LHC. The new pixel detector will cover a sensitive area of 13m$^2$. The pixel modules are loaded on light-weight carbon structures in the form of (half)rings and staves. Electrically functional prototypes of these local supports based on the RD53A readout chip were built and extensive...
A data conversion and compression ASIC, named LiTE-DTU, has been developed for the upgrade of the CMS electromagnetic calorimeter (ECAL) for the High-Luminosity phase of LHC. The ASIC integrates two 12-bit 160 MS/s ADCs, a data processing unit for gain selection and data compression, and a 1.28 Gb/s serializer.
The ASIC has been extensively tested in laboratory and in beam tests showing...
For the
-II upgrade of the ATLAS Muon Spectrometer to the High Luminosity LHC
(HL-LHC), a new first-level muon track trigger is needed to make use of the high momentum
resolution of the Monitored Drift Tube (MDT). The current front-end electronics of the MDT
chambers do not meet these conditions, they have to be replaced. Therefore, a new ASD2
ASIC chip has been developed. Finally, 50000...
A novel ultra-low-power front-end discriminator circuit for pixelized detectors, named pseudo-thyristor, is described. It is based on a positive feedback topology using regular CMOS transistors with zero static current, rather than constantly drawing current in typical discriminators. When a small charge is injected at the input, the circuit flips rapidly due to the positive feedback and...
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in...
The HGTD is a novel detector introduced to augment the new all-silicon Inner Tracker in the pseudo-rapidity range from 2.4 to 4.0, adding the capability to measure charged-particle trajectories in time as well as space.
A prototype of Peripheral Electronics Board (PEB), which supports up to 55 front-end modules with 12 lpGBT, 9 VTRx+ and 52 bPOL12v, is developed to work as a bridge between...
The Jiangmen Underground Neutrino Observatory (JUNO) aims to determine the neutrino mass hierarchy by detecting antineutrinos from nuclear reactors using a large liquid scintillator volume. The detector uses around 20,000 20-inch photomultiplier tubes powered and read out by two electronics readout systems: underwater and above water. The back-end card (BEC) is a crucial component of the...
The status of the development of the Level-0 endcap muon trigger system for the ATLAS experiment at the HL-LHC is presented. Integrations of the new trigger algorithms and the implementation with firmware on a new prototype of the trigger board (Sector Logic, SL) are also presented. Results from hardware tests of the SL prototype board and integration tests with the newly developed front-end...
The CMOS Monolithic Active Pixel Sensor MIMOSIS being developed for the CBM experiment at FAIR will combine a spatial resolution of 5 µm with a time stamp of 5 µs and operate at peak rates of 80 MHz/cm². The full-scale prototype MIMOSIS-1 met these specifications , and the recently submitted MIMOSIS-2 has addressed shortcomings identified during the dense test campaign. Both complex...
An increasing interest is growing towards reconfigurable processing systems embedded on the detector ASICs. Explorative work has been carried out to investigate Single-Event Upset (SEU) rates in open source RISC-V processors. The Ibex RISC-V core includes hardware security features that could detect SEUs in the core and alert the System-on-Chip (SoC) for possible malfunctions. This research...
The use of a radiation-hard microprocessor or the application of a System-on-Chip (SoC) design methodology has a considerable beneficial impact on the future design of ASICs within the HEP community. The STRV (SEU-tolerant-RISC-V) is a Triple Modular Redundancy (TMR) protected RSIC-V microprocessor designed to withstand Single Event Effects (SEE) and operate close to a beamline or interaction...
We present a new kind of sensors made of 5µm pixels using 6-metal TJ 180 nm technology. The pixels are interconnected among themselves to conducting lines with three directions 0°, 120° and -120°. Two neighbouring pixels are connected to different lines with different directions. The lines are connected to readout cells hosting current amplifier with its current comparator, together with the...
In the ALICE read-out and trigger system, the present GBT and CRU based solution will also serve for Run4 without major modifications. By now, the GBT protocol has been superseded by lpGBT, and the GBT ASIC is not available for new productions. Extensions of the ALICE system (e.g. the planned FoCal detector) will therefore require to use lpGBT while keeping the compatibility with the existing...
An HV-CMOS (High-Voltage CMOS) prototype detector for particle detection in high energy physics experiments, named UKRI-MPW0, has been developed. This chip implements a novel sensor cross-section optimised for biasing the chip from the backside only and achieves an unprecedented breakdown voltage (> 600 V). With such a high breakdown voltage, UKRI-MPW0 is expected to achieve much improved...
High Level Synthesis (HLS) of FPGA firmware using C/C++ has been popular in the design of upgrade trigger systems in High Energy Physics, allowing physicists with no previous firmware expertise to efficiently design digital systems. This presentation will describe the methodology of HLS designs, including comparison of basic building block design of HLS and Hardware Description language...
Targeting on low power consumption and high spatial resolution, the CPV-4 SOI pixel sensor requires about 100 transistors to implement the analog-digital mixed circuit functionality within a given pixel area around 16 um x 20 um. By utilizing 3D vertical integration, signal amplification and threshold discrimination are achieved in the lower-level circuitry, while hit information storage and...
The Minimum Ionizing Particle (MIP) Timing Detector (MTD) is introduced in the CMS experiment to measure the time of MIPs. The MTD consists of 432 Readout Units (RUs) in its barrel region (BTL), each powered by two Power Conversion Cards (PCC). PCCs host three radiation and magnetic field tolerant DC-DC converters. More than 1,000 PCCs will be produced to satisfy the assembly needs of BTL with...
Maintaining the required performance of the CMS electromagnetic calorimeter (ECAL) barrel at the High-Luminosity Large Hadron Collider (HL-LHC) requires the replacement of the entire on-detector electronics. 12240 new very front end (VFE) cards will amplify and digitize the signals of 62100 lead-tungstate crystals instrumented with avalanche photodiodes. The VFE cards host five channels of...
This paper reports the design and measurement results of a 768-channel of 14-bit analog to digital converters. Each channel’s layout pitch is only 8.5µm with a sampling rate from 40KS/s up to 100KS/s. Testing results show a crosstalk about only +/- 1 LSB. The architecture of the circuit and the structure of the layout make it extensible to exceptionally large format of detectors beyond 1000...
This study evaluates the lifetime and aging process of the aluminium electrolytic capacitors to be used in the new protection systems of the High Luminosity LHC superconducting magnets. The accelerated testing and analysis of several groups of capacitors aged for more than one year provided insights into their expected lifespan and aging process. The results obtained have practical...
The paper presents a Dual Use Driver (DUDE) that is a component designed for the “Demonstrator ASIC for Radiation-Tolerant Transmitter” in 28nm (DART28) and is developed in R&D programme on technologies for future experiments. The driver operates at 25.6Gbps and it allows to drive either 100Ω transmission lines and optical ring modulators in a Photonics Integrated Circuit. The driver includes...
The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. Almost 200,000 chips have been tested with a production test system capable of exercising the majority of the ASIC functionality to ensure its correct operation.
Furthermore, specific individual qualification tests were carried...
The CMS Tracker Phase-2 Upgrade requires the production of new sensor modules to cope with the requirements of the HL-LHC. The two main building blocks of the Outer Tracker are the Strip-Strip (2S) and Pixel-Strip (PS) modules. All-together 47520 hybrid circuits will be produced to construct 8000 2S and 5880 PS modules. The circuit designs for the mass production were fine tuned and the...
We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase-Locked Loop under a 63 MeV proton beam of instantaneous fluence 10^10 protons/cm²/s. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) for the High-Luminosity Large Hadron Collider (HL-LHC). Observed...
For the construction of the future ATLAS strip tracker end-caps, six geometries of silicon strip detector modules were designed. Each module comprises one or two silicon strip sensors and several flexes holding the required readout electronics, designed to match the geometry of each module. Due to the large number of designs, two module geometries using two sensors per ring module were...
This work introduces AI-In-Pixel-65, an ROIC test chip designed for pixelated X-ray detectors using a 65nm Low Power CMOS process. The study compares two data compression techniques, Principal Component Analysis (PCA) and AutoEncoder (AE), implemented within the chip's pixelated area to address I/O bottlenecks. Our design methodology utilizes high-level synthesis (HLS) and hls4ml, offering...
The combination of 3D tracking and high-precision timing measurements has been identified by the European Committee for Future Accelerators as a fundamental requirement to increase detection capabilities for future applications. Among others, on-chip high-quality clock is a key factor determining the overall resolution of Timing ASICs. However, in large and dense chips, power-grid drops can...
The design of a new DC/DC power converter capable of being integrated with a detector is described. It works in harsh environment and can supply up to 170 W per channel. Up to four modules, each one equipped with 8 channels, can be accommodated in a water-cooled compact crate with a small volume of 24 dm^3. Its electrical, environmental and thermal performance is detailed here.
The Electric Field Detector (EFD-02) on board of the second China Seismo-Electromagnetic Satellite (CSES-02) will measure the ionospheric electric field components at a Low Earth Orbit (LEO) over a wide frequency band (DC - 3.75 MHz) and with less than 1 \muV/m/\sqrt{Hz} sensitivity. EFD-02 will measure the voltage differences between pairs of probes installed at the tips of four booms...
HEPS-BPIX40 is a new hybrid pixel detector for the High Energy Photon Source in China. It is a full upgrade from BPIX20, with a 128 x 96 pixel matrix and 140 μm x 140 μm pixel size. The circuit operates in single photon counting mode with dual thresholds and programmable gains. The tested frame rate is 2 kHz in continuous readout mode. A detector module covers 3.7 cm x 8.1 cm and consists of 2...
We present the design and performance of the new On-Board electronic for the Drift Tubes (OBDT) for the superlayer theta along the direction parallel to the beam-line, built to substitute part of CMS DT Muon on-detector electronics. The OBDT-theta is responsible of the time digitization of DT chamber signals for the theta view, allowing further barrel muons tracking and triggering. It's also...
The ePIC experiment at the future Electron-Ion Collider aims to use silicon photomultipliers as the photodetector technology for the dual-radiator ring-imaging Cherenkov detector (d-RICH). Despite their advantages for this low light application in high magnetic fields, SiPMs are sensitive to radiation and require rigorous testing to ensure that their single-photon counting capabilities and...
For the High Luminosity-Large Hadron Colider (HL-LHC) phase, the ATLAS Tile Calorimeter (TileCal) is undergoing a major upgrade with a complete redesign of the on- and off-detector electronics. In the new readout architecture, the calorimeter signals are digitised every 25 ns directly on-detector and transferred to the off-detector Tile PreProcessor (TilePPr) via high-speed optical links. The...
ALICE ITS3 is a novel vertex detector replacing the innermost layers of ITS2 during LS3. Composed of three truly cylindrical layers of wafer-sized 65 nm stitched Monolithic Active Pixel Sensors, ITS3 provides high-resolution tracking of charged particles generated in heavy-ion collisions. This contribution presents an overview of the ITS3 detector, highlighting its design features, integration...
The Serenity-S1 is a Xilinx VU13P based Advanced Telecommunications Computing Architecture (ATCA) processing blade that has been optimised for production. It incorporates many developments from prototype cards and where possible adopts solutions being used across CERN. It uses many new parts because commonly used parts have disappeared from the market during the semiconductor crisis with only...
New advanced front end electronics are designed for the improved RPCs of CMS experiment for data taking during HL-LHC era. This electronics is developed to read out the RPC detectors from both ends of a signal strip, using a new ASIC, iRPCROC, which triggers the Cyclone V FPGA to record the timing information, allowing the correct identification of the position along it. The on-chamber results...
The the LHCb collaboration proposes a Phase-II Upgrade of the detector, to be installed during the LHC Long Shutdown 4. Currently, the VELO collaboration is exploring new sensor technologies, and the benefits that would derive from adding a time stamp to the track reconstruction. The most recent advances in this field, and the potential candidates that can meet the VELO Upgrade-II...
The LHCb Experiment is commissioning its first upgrade to cope with increased luminosities of LHC Run3, being able to improve on many world-best physics measurements. A new tracker based on scintillating fibers (SciFi) replaced Outer and Inner Trackers delivering an improved spatial resolution for the new LHCb trigger-less era, with a readout capable of reading ~524k channels at 40MHz. Fully...
For the high-luminosity upgrade of the ATLAS Inner Tracking detector, a new pixel detector will be installed to allow for a bigger bandwidth and cope with the increased radiation among other challenges. This contribution will present the evaluation of the Outer Barrel Pixel layer services chains. A full data transmission study covering data merging will be presented from the pixel module all...
Early measurements on monolithic pixel sensor prototypes in the TPSCo 65nm technology indicate a different response and radiation tolerance (up to $5\times10^{15}~1\text{MeV}~\text{n}_{\text{eq}}/\text{cm}^2$) for different sensor layout and process variants, illustrating the importance of layout and process in the path towards increased sensor radiation tolerance. Using these measurement...
To cope with the increase of the LHC instantaneous luminosity, new trigger readout electronics were installed on the ATLAS Liquid Argon Calorimeters.
On the detector, 124 new electronic boards digitise 10 times more signals than the legacy system. Downstream, large FPGAs are processing up to 20 Tbps of data to compute the deposited energies. Moreover, a new control and monitoring...
The radiation hardness of transistors in a 22nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2 ) with different back-gate bias configurations, up to 2 V. The...
The upcoming ProtoDUNE-II program at the CERN neutrino platform will consist of 2 liquid argon time projection chambers, which will serve as demonstrators of the technologies that will be used in the first 2 far detectors of the Deep Underground Neutrino Experiment (DUNE). A core component of these detectors is the cryogenic charge readout electronics, which are immersed in liquid argon along...
The construction of the ATLAS strip tracker barrel will require the assembly of 12,000 barrel detector modules over the course of 3.5 years. In 2022, during the module pre-production phase, modules were found to display clusters of noisy channels outside required specifications when tested at operating temperatures (-40 ºC), called “Cold Noise”. Extensive investigations into the cause and...
The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics, atomic physics, interdisciplinary science, and relative applications. A Common Readout Unit (CRU) has been designed for HIRFL-CSR to reduce the development time, production cost, and maintenance difficulties of the data transmission at HIRFL. With the Xilinx the Virtex 7...
This contribution presents a pragmatic approach to read-out electronics for drift chambers used in particle physics experiments, specifically for the R3B experiment at GSI. The proposed circuit design uses discrete miniature SMD components and LVDS inputs of a low-cost FPGA to achieve a performance similar to the classic ASD8 ASIC. The presented approach offers an attractive solution for small...
In this work, a low-power low-noise readout circuit for monolithic pixel detectors is presented. The design focuses on robustness and scalability for both reticle sized chips and stitched designs. The front-end includes a differential charge sensitive amplifier, a reset network and a two-stage discriminator. Threshold trimming is performed with a 3-bit DAC. The feedback capacitance is kept at...
Beam monitor is a sub detector for the CSR external-target experiment (CEE) at HIRFL, which is designed to monitor the beam status. A custom-designed pixel chip Topmetal-CEEv1 acts as the sensor for locating the position of each particle. In this paper, we present a prototype readout system for beam monitor. Injected pulse test and 241Am alpha test in the laboratory as well as beam test at...
The ASIC Design Group at RAL has commenced a three-year programme developing radiation-hardened 28nm circuits intended to provide verified building blocks for future projects. The aim of this programme is to complement and add to the CERN common IP library for 28nm. Our programme includes a range of utility circuits such as high precision amplifiers, a low power 12bit ADC for housekeeping,...
During the ATLAS phase II upgrade, the tracking system of the ATLAS experiment will be replaced by an all-silicon detector called the inner tracker (ITK) with a pixel detector as the most inner part. The monitoring data of the new system will be aggregated from an on-detector ASIC called Monitoring Of Pixel System (MOPS) and sent to the Detector Control System (DCS) using a new interface...
The HGTD aims to mitigate the effect of large pile-up interactions in the ATLAS Phase II upgrade project by providing accurate time measurements for tracks. However, since HGTD readout modules are unavailable during early stage, an FPGA-based front-end module emulator is designed as a substitute for system testing. This emulator also provides a flexible and cost-effective means to verify the...
The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype, TaichuPix, based on a column drain readout architecture, has been implemented to achieve high spatial resolution and fast readout. A 6-layer telescope made by TaichuPix-3 chips and baseline vertex...
Upgraded version of the CMS electromagnetic calorimeter (ECAL) Front-End (FE) card is designed to provide the lossless data streaming and reliable control and synchronization of the on-detector Very-Front-End (VFE) units.
The initial card design, validated in the beam tests in 2018-2019, was significantly modified to support the fast and reliable access to the VFE cards components for...
The Phase-2 Upgrade of the CMS Outer Tracker requires the production of 8000 Strip-Strip and 5880 Pixel-Strip modules, altogether incorporating 47520 hybrid circuits of 15 variants. Module design makes the potential repairs unfeasible; therefore, performing production-scale testing of the hybrids is essential. Accordingly, a scalable, crate-based test system was designed and manufactured,...
This contribution presents the latest advancements in integrating the Upstream Tracker in LHCb, including deploying control software, data acquisition firmware, decoding algorithm, and data analysis software. Additionally, the progress of different tasks is detailed, along with plans for the immediate future. The main focus of this talk is on the assessment of detector performance, including...
The Micro Vertex Detector is a key component of the PANDA experiment at FAIR. This contribution focuses on the development of the Module Data Concentrator (MDC) ASIC for the configuration, time distribution and readout of the silicon microstrip subdetector system of the PANDA Micro-Vertex Detector (MVD). A first version of the MDC architecture has been developed on FPGA and integrated with the...
NνDEx is a proposed experiment to hunt for the neutrinoless double beta decay of 82Se, with a high pressure SeF6 gaseous TPC. The readout and DAQ system are important parts of the experiment. The readout plane placed in one endcap of the TPC consists of around 15,000 sensors for charge measurement. It is crucial to read out data from all of these sensors efficiently. This paper will introduce...
The High-Luminosity LHC upgrade will have a new trigger system that utilizes detailed information from sub-detectors at the bunch crossing rate, which enables the Global Trigger (GT) to use high-precision trigger objects. Novel machine learning-based algorithms will also be included in the trigger system to achieve higher selection efficiency and detect unexpected signals. The focus of this...
In this work, we present the design, test system, and measurement results of the SMAUG_ND_1 ASIC. The described circuit implements an indirect energy measurement algorithm based on noise distribution measurement. The algorithm is similar to the threshold scan procedure but is done with a single pulse. The chip implements the matrix of 7x7 pixels each with 8 independent comparators and a size...
One of the main objectives of the Taishan Antineutrino Observatory (TAO) is to accurately measure the reactor neutrino energy spectrum to provide precise input to the Jiangmen Underground Neutrino Observatory (JUNO). In this study, we designed a full potential readout system for TAO based on the Klaus6 chip.We also developed a mockup prototype based on the design, which includes 4 chips (up to...
In this article we describe the measurement results on an “AARDVARC” prototype in 130 nm. AARDVARC is a multi-channel waveform digitizing and processing Application Specific Integrated Circuit (ASIC) front-end. We report on various performance metrics: fast sampling (10-14 Gsa/s), deep storage (32K samples), timing resolution (better than 5ps), low power consumption (<100mW/channel).
FABulous is an open-source eFPGA framework developed by the University of Manchester, enabling programmable digital logic to be integrated into ASIC designs. In 2023, our team plans to submit a 28nm CMOS ASIC and explore flatten versus hierarchical design using HVT devices for radiation hardening. This 28nm eFPGA design will use SUGOI and PGPv4 to program and move data in and out of the eFPGA....
The ALICE experiment at the CERN LHC will replace the three innermost layers of the Inner Tracker System (ITS) with an innovative vertexing detector. A single-die stitched monolithic pixel detector of 1.8 cm x 26 cm designed in 65 nm CMOS imaging technology will be used to build these layers. The data communication is done via the 1.8 cm edge of the detector. This contribution will focus on...
The drift chambers of the HADES spectrometer at GSI, Darmstadt/Germany, form its main tracking system. Designed more than twenty years ago, the whole front-end electronics chain is being replaced with state-of-the-art electronics.
The new analog signal processing is based on the PASTTREC ASIC, developed for the PANDA Straw Tube Tracker. The digitization of data happens in FPGA-based...
Crilin – a semi-homogeneous, longitudinally segmented highly granular electromagnetic calorimeter with Cherenkov PbF2 crystals has excellent timing and improved radiation resistance. A two-channel front-end prototype was tested at CERN-H2 with 120 GeV e- using PbF2 and PWO-UF crystals, yielding a single-cel timing resolution <30 ps for energy deposits <3 GeV. Crilin prototype consists of two...
The MicroTCA standard is widely used in the field of particle physics, and Advanced Mezzanine Card is the basic component of the MicroTCA system that requires module management control (MMC) for management. RISC-V is an open source ISA (Instruction Set Architecture) with extensive use. In this paper, we implement the MMC firmware on the MCU with RISC-V architecture. We build a universal...
Digital circuits exposed to radiation, e.g. at HL-LHC, are equipped with radiation-hardening features such as triple modular redundancy and error-correction codes. A method is developed to measure the single-event-upset cross section from error rate measurements in register banks that are protected by both ECC and TMR, taking into account the non-linear relationship between the cross section...
A new HV-CMOS pixel chip, called MightyPix, is being developed for the Mighty Tracker, an upgrade planned for LHCb in anticipation of the HL-LHC. Extensive research is ongoing to study the tracks and occupancy at the Mighty Tracker. This data is now used to simulate MightyPix’s performance in the LHCb environment, with focus on the digital readout. First results show an efficiency of 99.7% for...
The Mu2e CsI crystal calorimeter has high granularity, 10% energy and 500 ps timing resolution for 100 MeV electrons, and will achieve extremely high levels of reliability and stability and in a harsh operating environment. Each crystal is readout by two custom UV-extended SiPMs, with independent readout channels, coupled to custom front-end electronics boards, to provide individually...
In this contribution, we present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics...
We will report the performance of Topmetal-S chip, a charge sensor specifically designed to directly sense ions for the high-pressure ion TPC of N$\nu$DEx experiment for neutrinoless double-beta decay search.The signal waveforms were investigated with various experiments and chip configurations.The equivalent noise charge of Topmetal-S is measured to be 120 e$^{-}$.Different ions species, both...
The interplay between High Energy Physics and Positron Emission Tomography detector development keeps providing encouraging outcomes of mutual interest, most notably observed in the development of scintillators, photon detectors, as well as the physics simulation tools. Our group develops PET detectors with the time of flight ability. In this work we present the 16-channel prototype which uses...
The consolidation of the Large Hadron Collider (LHC) beam position monitor (BPM) requires the deployment of about 5000 single-mode radiation-tolerant optical transmitters, working at 10 Gbps during 20 years of operation. While the use of the custom devices being designed at CERN remains the baseline for the project, 8 commercial of the shelf (COTS) optical transceivers have been evaluated as...
The MUX64 ASIC is a 64-to-1 analog multiplexer developed to expand the ADC input channels in the peripheral electronics of HGTD for the ATLAS Phase-II upgrade. The MUX64 chips will be used in the radiation field of high-luminosity pp collisions at LHC to an integrated luminosity of 4000 fb-1. The radiation hardness of MUX64 have been tested with 80 MeV protons and X-ray exposures...
Thirty-four RD53a Pixel detector modules arriving from different assembly sites are received at CERN in order to be integrated into the ITk demonstrator. The modules will go through different production validation stages, to monitor any performance degradation before the last stage with a full system test on the demonstrator. To mimic real detector services, multiple modules integrated on...
A charge-redistribution ADC with 10-bit resolution is implemented in the TPSCo 65nm CMOS process. The design is intended for flexible on-demand monitoring of vital system signals, such as temperature, in MAPS detectors. The successive approximation principle is implemented using only two matched capacitors and a trimming DAC, while an internal clock generator and digital sequencer are used to...
Advances in timing detector technology require new specialized readout electronics. Applications demand high rep rates, below 10 ps time of arrival resolution and, low power. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc. in collaboration with UC Santa Cruz has developed a prototype SiGe...
We report on our current developments towards a silicon photonic, 4-channel wavelength division multiplexed transmitter system with planar fiber chip coupling. The optical core components consisting of the photonic chip and the connecting V-groove mounted glass fibers were assembled with sub-micrometer accuracy on a glass plate with low thermal expansion for a stable fiber chip coupling. This...
After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the High Luminosity-LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs optical-...
This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout a wide range of detectors like Photomultiplier Tubes, to be used at the LHC Run 4 or SiPMs, candidates for Run 5. The front-end (FE) stage has an input impedance (Zin) below 50 Ω and an input dynamic range from 5 µA...
The ATLAS Strip Tracker for HL-LHC consists of individual modules that host silicon sensors and front-end electronics. The modules are then mounted on carbon-fiber substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card connects up to 28 data lines to the lpGBT and VL+ ASICs that provide data serialization and 10 GBit/s optical data transmission to the off-detector...
We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment. The FBCM system should provide reliable luminosity measurement with 1ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises six channels of fast preamplifier working in transimpedance...
The ATLAS level-1 calorimeter trigger is a custom-built hardware system
that identifies events containing calorimeter-based physics objects,
including electrons, photons, taus, jets, and missing transverse energy.
In Run 3, L1Calo has been upgraded to process higher granularity
input data. The new trigger, currently running in parallel with the
legacy system, comprises several...
The assembly of the ATLAS Inner Tracker requires the construction of 19,000 silicon strip sensor detector modules in eight different geometries. Modules will be assembled and tested at 31 institutes on four continents, from sensors, readout chips and flexes. In order to adhere to the module specifications defined for sufficient tracking performance, a rigorous programme of quality control and...
The design of HVCMOS pixel detectors for measuring Galactic Cosmic Rays (GCR) and Solar Energetic Particles (SEP) in space is presented. The design goals are: (a) cover a very wide dynamic range (from ~0.5fC to pC) and (b) minimize the power consumption. Two pixel designs were implemented, one tailored to the measurement of high energy depositions due to impinging ions and one with high gain...
ECAL Barrel (EB) and MTD Barrel Timing Layer (BTL) subdetectors of the CMS are approaching series production of electronic boards, including voltage conditioning PCBs: LVR and PCC respectively. 2448 LVRs and 864 PCCs will be installed during LS3 of the LHC. These boards are hosting radiation-tolerant bPOL12V ASICs which convert a broad input voltage range into required voltage levels for...
The electronic systems at CERN, exposed to the harsh radiation environments of particle accelerators and experiments, require specific qualification procedures to ensure reliability under radiation. A large number of distributed systems, thermal neutron fluences in shielded areas, and spectra composed mainly of neutrons are some of the unique challenges that the LHC presents. CERN has...
The PADME experiment at LNF-INFN employs positron-on-target-annihilation technique to search for new light particles. Crucial part of the experiment are the charged particle detectors, composed of plastic scintillator bars with light transmitted by wavelength shifting fibers to silicon photomultipliers (SiPM). The location of the detector – close to a turbomolecular pump, inside a vacuum tank,...
The CHARM Radiation Tolerant Tester Board (CRATEBO) is a testing platform for the CERN High-energy Accelerator (CHARM) irradiation facility. It is meant to ease the radiation testing of FPGA-based systems by providing users with a radiation-tolerant carrier card for the Device Under Test (DUT). It provides a high-speed communication interface, a flexible power supply, and DUT connections via a...
For optimal operations in the high radiation and pileup environment of the HL-LHC, the CMS-HGCAL requires precise timing information at the level of 30ps (RMS) for a particle shower. The time measurement in Silicon detector modules is performed using a per-channel time-of-arrival discriminator coupled with charge measurement to correct for the time-walk. The module design includes...
The characterization of compact non-traveling-wave Mach-Zehnder modulators (NTW-MZMs) for optical readout in high-energy physics experiments will be presented to provide power-efficient alternatives to conventional traveling-wave devices and a more resilient operation compared to ring modulators. Electro-optical small-signal and large-signal measurements will be reported to show the...
