Speaker
Description
The CMOS Monolithic Active Pixel Sensor MIMOSIS being developed for the CBM experiment at FAIR will combine a spatial resolution of 5 µm with a time stamp of 5 µs and operate at peak rates of 80 MHz/cm². The full-scale prototype MIMOSIS-1 met these specifications , and the recently submitted MIMOSIS-2 has addressed shortcomings identified during the dense test campaign. Both complex mixed-signal circuits were developed using the Digital on Top methodology. We present the sensor design, introduce our design methodology and discuss the lessons learned during the design process.
Summary (500 words)
Compressed Baryonic Matter (CBM) will be one of the core experiments of the future Facility for Antiproton and Ion Research (FAIR) in Darmstadt. The fixed target heavy ion experiment aims to explore the QCD phase diagram in the region of high baryon densities. The mission of its Micro-Vertex Detector (MVD) includes the determination of the secondary decay vertices, the background rejection in dielectron spectroscopy and the reconstruction of weak decays. It will consist of nearly 300 CMOS Monolithic Active Pixel Sensor (MAPS) arranged in 4 double-sided stations operating in the target vacuum of the experiment.
The dedicated CMOS Monolithic Active Pixel Sensor, called MIMOSIS, is being developed at the IPHC Strasbourg, the Goethe University Frankfurt and GSI. It is inspired by the ALPIDE sensor designed for the ALICE-ITS2, but had to be improved by one order of magnitude in terms of rate capability and radiation tolerance to meet the requirements of the CBM experiment. This required a redesign of the internal data acquisition architecture, i.e. the digital data compression and transfer logic, in order to cope with an internal peak data flow of up to 20 Gbits/sec. This flow is averaged out by an elastic buffer that allows the sensor output throughput to be limited to 2.56 Gbps. Despite the high data rate capability of this large sensor with an active area of almost 1x3 cm², the power consumption remains as low as 50 mW/cm² at a frame rate of 200 kframe/s. This low power density is required due to the vacuum operation of the detector.
A first full-scale prototype, called MIMOISIS-1, has been developed in the 180 nm CMOS Imaging Sensor process of Tower Semiconductor, taking advantage of the deep p-well feature that allows digital circuitry to be integrated into the sensitive pixel matrix without reducing charge collection efficiency. This process has been modified to achieve full depletion of the epitaxial layer to increase radiation hardness. The sensor meets the main requirements expected from the experiment. A second prototype, MIMOSIS-2, was developed to improve the functionality of the chip and to fix some minor bugs.
Although the design of both sensors is based on the Digital on Top methodology, a complete re-foundation of the design flow had to be implemented to overcome the limitations of the first approach (turnaround time, timing closure, full flat verifications, …). In addition, the second prototype was designed using the Stylus Flowkit, a flow structure that allows users to run all Cadence digital tools. The flow was adapted to allow full flat timing and power verification of the 31.1 x 17.2 mm² sensor.
This contribution introduces the design of the sensor and discusses in detail the methods used, their limitations and the lessons learnt in applying them to the design of a reticule-sized CMOS Pixel Sensor.
