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Description
H2GCROC is the 130nm CMOS ASIC designed to read out the SiPMs coupled to the scintillating tiles of the back hadronic sections of CMS HGCAL (High Granularity Calorimeter). Each of its 72 channels is composed of a current conveyor, a high-gain preamplifier, a shaper, and ADC to read the energy, with two discriminators connected to TDCs for time-of-arrival and time-over-threshold information, respectively. This work presents the ASIC architecture and its characterization in lab and test beam, proving good adaptability in calibration, radiation tolerance, capacity to measure SiPM SPS (single-photon-spectrum), MIP's time and energy with high resolution.
Summary (500 words)
H2GCROC is a radiation-hardened 130 nm CMOS chip developed by OMEGA, AGH, CEA, and CERN to read the energy and time of the SiPM-on-tile detectors of CMS HGCAL. It has 78 channels and dissipates 15 mW per channel.
Each channel contains a current conveyor, a low-noise preamplifier, and a shaper connected to a 10-bit 40 MHz SAR-ADC, allowing charge measurement over the preamplifier's linear range. A discriminator and a TDC provide charge information from time-over-threshold (ToT) over a 200 ns dynamic range in the preamplifier's saturation zone. Additionally, a fast discriminator and TDC produce timing information with an accuracy of 25 ps. The ASIC uses a DRAM memory to store charge and timing data and performs the data processing to select and compress the meaningful data to send. It is configurable with an I2C protocol for slow control and fast commands at 320 MHz.
The main challenge in the design of this ASIC was on the adaptability to read the MIP signal with a high dynamic range of charge measurement (160 fC to 320 pC) and at the same time be able to calibrate and quantify the SiPM-on-tile performance using the SPS (single-photon-spectrum) technique without sacrificing a lot in precision and time resolution. Furthermore, the ASIC needs to have a good radiation tolerance and be able to compensate for the SiPM radiation damage during the entire lifetime of HGCAL. The tiles of HGCAL will use different sizes of SiPM up to 9mm². Therefore, the design and calibration process considered the effects of capacitance, rising, and falling time of different SiPM sensors.
The gain of each block of the Front-end design can be calibrated for the MIP to have good linearity and to adapt to the dynamic range. In addition, the channel's dispersion can be compensated with internal DACs considering the breakdown voltage variations of SiPMs, temperature changes, and production tolerances. Also, the ASIC includes a calibration circuit that injects up to 200 pC of charge internally into each channel.
The chip was extensively tested in the lab and test beam and has proved its good performance in fulfilling the requirements for reading the SiPM-on-tile of HGCAL. This work examines the ASIC front-end design and its performance with different SiPM detectors. After full calibration, two chip configurations are proposed, one for in-situ calibration after installation of HGCAL and a configuration for HGCAL operation.
The two plots attached to this summary prove in Figure 1 the capability of the ASIC to perform SPS measurements, whereas Figure 2 displays the energy and time-of-arrival (ToA) measurements for small charge injection. The tests performed with the third fabricated version of the ASIC are encouraging. Only minor corrections will be needed for the final version to be ready for the CMS experiment.
