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Description
In the context of the Strategic R&D on Technologies for Future Experiments, the sensitivity to single-event-effects of a commercial 28nm CMOS technology was investigated through heavy-ion and proton tests. Two chips were designed to study single- and multi-bit-upset, single-event-transient and single-event-latch-up. Bit upsets were studied on both D-Flip-Flops and foundry SRAMs. LET of heavy ions ranged from 1.3 to 88.39 MeV/mg/cm2, with fluences of 5e6 ions/cm2 for each LET. Protons at 350 and 480-MeV were used. These results provide a comprehensive overview of the SEU sensitivity of the selected 28nm node, representing a milestone in its qualification for HEP applications.
Summary (500 words)
In the context of the Strategic R&D on Technologies for Future Experiments, the IC Technology Work Package 5 at CERN (WP5) has targeted 28nm CMOS process as common technology for the most advanced developments for High Energy Physics (HEP) applications. For this reason, a family of 3 ASICs, called EXPloit28 (EXP28), has been designed to study radiation effects on 28nm CMOS technology. This work reports the results of heavy-ions (HI) and proton irradiation campaigns performed on the two of the three chips in the EXP28 family designed for assessing the sensitivity of this technology to Single Event Effects (SEEs).
The first chip (EXP28-SEE) contains structures for studying single-event-transient (SET) and single-event-upset (SEU). The circuit to study SET is based on a vernier detector that allows measuring the cross-section for transients, estimate transient length and detect multiple transients. Rate and cross-section of SEUs are assessed thanks to 7 matrices of 4096 D-Flip-Flop (DFF), with different threshold-voltage flavours, driving strengths and spacing among the DFFs, and 4 different foundry SRAM types (Single, Single Ultra-High-Density, Dual, Dual Ultra-High-Density).
The second chip (EXP28-ANA) is designed to study Single-Event-Latch-up (SEL). The SEL detector includes both digital and analog structures to evaluate the minimum distance between substrate contacts (taps) needed to prevent SEL.
The HI test was performed at the Heavy Ion Facility (HIF) of UCLouvain. The EXP28-SEE chip was tested for all available ions, at an incident angle of 0° and 45° and at a fluence of 5e6 ions/cm2 for each ion-angle combination. LET ranged from 1.3 MeV/mg/cm2 to 88.39 MeV/mg/cm2.
SET length has shown to increase with LET, ranging from ~70 to ~180 ps. Multi-SET were measured only for LET ≥ 62.5 MeV/mg/cm2.
After a LET ≈ 20 MeV/mg/cm2, errors in SRAMs are dominated by multi-bit-upsets (MBU). These results are confirmed in the DFF structure, where MBUs represent a large fraction of the measured errors. However, no MBU is measured in the matrix with a distance between FF of 5um. This extremely important result provides the first indication of the minimum distance to avoid MBU, a crucial piece of information in triplication strategies.
The EXP28-ANA was tested with LET ranging from 20.4 to 241.48 MeV/mg/cm2 and a total fluence of 166.75e6 ions/cm2. No SELs were measured in any of the 28 analog and 12 digital structures, even when the supply voltage was increased to 115% of its nominal value.
Protons at 350 and 480-MeV, with a total fluence of 3.39e12 p/cm2, were used to test 2 EXP28-SEE chips at the TRIUMF facility in Canada. Proton energy had little impact on the results.
Results show an SET length of 90±15 ps, with 81 total hits.
The percentage of MBUs in SRAMs was ~30% regardless of the SRAM type. No MBUs were measured for protons when the distance between FFs was larger than 5um.
These results provide a comprehensive overview of the SEU sensitivity of 28nm CMOS technology, representing a milestone in its qualification for HEP applications.
