Speaker
Description
The baseline architecture for the ATLAS Phase-II upgrade has a single-level hardware trigger (Level-0 Trigger) with a maximum rate of 1 MHz and 10 μs latency. A full-function Global Common Module (GCM) prototype has been designed and implemented for the core part of the Level-0 Trigger, the Global Trigger. This GCM features two of the latest Adaptive Compute Acceleration Platform (ACAP) devices from Xilinx, the Versal Premium VP1802, plus twenty 12-channel 25.7 Gb/s FireFly optical engines. Presented here is the design process of this full-function GCM prototype hardware, with the focus on the technology choices and simulation results.
Summary (500 words)
The High Luminosity Large Hadron Collider (HL-LHC), an upgrade of the LHC, is scheduled to be operational from 2029. It aims to achieve instantaneous luminosities of a factor 5–7.5 larger than the LHC nominal value, thereby enabling physicists to study known mechanisms, such as the Higgs boson, in greater detail, and potentially observe rare new phenomena. However, realizing the physics potential of this much higher luminosity requires an increase in the bandwidth of data processed by ATLAS of an order of magnitude. This presents significant challenges to the design of the Trigger and Data Acquisition systems. A baseline architecture, based on a single-level hardware trigger (Level-0 Trigger) with a maximum rate of 1 MHz and 10 μs latency, has been proposed for the ATLAS Phase-II upgrade to meet these challenges. The Level-0 Trigger includes a brand-new subsystem, the Global Trigger, which performs algorithms similar to those used offline at Phase-I (such as Topoclustering) on full-granularity calorimeter data.
The Global Trigger architecture is divided into three layers: the Multiplexer Processor (MUX) layer, the Global Event Processor (GEP) layer, and the Global to Central Trigger Processor interface (gCTPi). The MUX layer collects data from detectors (calorimeter and muon) and legacy Feature Extractor modules, time-multiplexes them bunch-crossing by bunch-crossing and sends full events to the GEP layer in a round-robin fashion. Each GEP node in the GEP layer receives the full event data pertaining to a particular bunch-crossing, executes complex algorithms, and sends the results to the gCTPi, which comprises a single node that selects and resynchronises the results from all GEP nodes before sending them to the CTP.
A common hardware approach has been taken in the Global Trigger to simplify its system design and long-term maintenance, and a full-function Global Common Module (GCM) prototype has been designed and implemented to fulfil the functionalities of MUX, GEP and gCTPi with different firmware loads. Recent firmware study shows that the programmable logic resource requirement of the GEP node is beyond that of the Ultrascale+ device XCVU13P used on previous demonstrators. This GCM prototype features two Xilinx Versal Premium ACAP VP1802, which has double the density of the XCVU13P and includes an integrated SoC with a completely new architecture. All the high-speed I/Os on the GCM are handled with twenty 12-channel 25.7 Gb/s FireFly optical engines. The Global system design has been optimised to limit the GCM power consumption to a maximum of 400 W, which fits within ATLAS ATCA shelf cooling capability. Power design, high-speed signal design and thermal design are the three biggest challenges that the GCM hardware development is faced with. A 26-layer PCB with low-loss material, vias in pads and backdrill technologies has been used for this GCM board. Extensive PCB simulation and thermal simulation have been undertaken to guide its layout design to ensure power integrity, signal integrity and thermal performance.
This talk presents the design process of this full function GCM prototype hardware with the focus on the technology choices and simulation results.
