Speaker
Description
A data conversion and compression ASIC, named LiTE-DTU, has been developed for the upgrade of the CMS electromagnetic calorimeter (ECAL) for the High-Luminosity phase of LHC. The ASIC integrates two 12-bit 160 MS/s ADCs, a data processing unit for gain selection and data compression, and a 1.28 Gb/s serializer.
The ASIC has been extensively tested in laboratory and in beam tests showing excellent yield and performance. The radiation tolerance has been verified with dedicated test campaigns for both total ionizing dose and single event effects. Results from these tests, showing the design readiness for mass production, will be presented.
Summary (500 words)
The challenging conditions of the high luminosity upgrade of LHC (HL-LHC) have required a full re-design of the CMS electromagnetic calorimeter (ECAL) front-end electronics. The Very Front-End cards will be equipped with two new ASICs: a fast trans-impedance amplifier (CATIA) and a data conversion and compression ASIC (LiTE-DTU). CATIA is trans-impedance amplifier to read the signals from the APD sensors coupled with the ECAL crystals. It features two differential outputs with different gains to ensure optimal resolution for signals up to 2 TeV. Designed in a commercial CMOS 65 nm technology, the LiTE-DTU ASIC integrates two 12-bit SAR ADCs to sample the CATIA outputs at 160 MHz. A gain selection mechanism and a lossless data compression algorithm allow data to be transmitted using only one 1.28 Gb/s serializer. The low-jitter 1.28 GHz clock, required by the ADCs and the serializer, is generated by an on-chip PLL.
This upgrade will ensure high-precision energy measurements for the HL-LHC phase and the improved time resolution, of about 30 ps for photons and electrons above 50 GeV, will cope with the increased pileup events and enhance the rejection of spike signals produced from direct interaction with the APDs.
The LiTE-DTU ASIC has been extensively tested both in laboratory and beam tests and the pre-production version of the ASIC has shown excellent performance. An ADC ENOB of 9.4 has been measured at 50 MHz input frequency. This value, obtained using the internal PLL clock, is slightly lower than the design value of 10.2. Measurements using an external clock source and providing an ENOB of 10.2 indicate that this degradation is due to the PLL clock jitter. The overall performance is already adequate for the system requirements, nevertheless the PLL clock jitter will be improved in the ASIC next version.
Radiation tests have been performed to assess the LiTE-DTU tolerance to total ionizing dose (TID) damage with 10-keV X-rays up to 50 kGy and no variation has been observed in the performance of the ASIC after irradiation. The LiTE-DTU has been tested also for single event upsets (SEU) tolerance with a measured cross section of about 6.8·10^(−18)cm^2/bit for the I2C registers and 9.4·10^(−13)cm^2/chip for the data path, which is significantly higher as the ADC data registers are not SEU-protected. These results are more than adequate for the CMS experiment.
A 600 dies pre-production has been employed to equip a 400 channels ECAL module for large-scale integration tests and measure the performance and stability of the full readout chain. These chips have been tested and validated using an automated procedure with a yield of about 97%. This test setup features a test board with a ZIF socket, a commercial FPGA board, a low-jitter clock generator and two arbitrary waveform generators. All the modules are remotely controlled by a custom DAQ test interface written in Python. This system will be embedded in the automatic test equipment for the test and validation of the LiTE-DTU mass production which will deliver about 100k chips and is foreseen in May 2023.
