Speakers
Description
A new silicon tracker detector (ITS3) will be installed in ALICE Inner Tracking System during the LHC long shutdown 3. We develop a 10.24Gbps Data Serializer and Wireline Transmitter (GWT-PSI) circuit for the readout of the detector. A 16-to-1 multiplexer architecture achieves low power consumption (28mW) and avoids high-frequency (> 640MHz) clock signals in the circuit. A clock-cleaning PLL and power-supply cleaning LDO will be built into the circuit making it immune to the noisy operation environment. A prototype has been submitted in the ER1 production run in the TPSCo 65nm ISC CMOS imaging technology.
Summary (500 words)
The ITS3 detector will comprise 6 stitched wafer-scale chips (280 mm long). Each chip is a pixelized Monolithic Active Pixel Sensor (MAPS) . 6 high-speed data transmission links will be implemented per chip to read out up to 46Gb/s per chip. The data transmission link serializer will convert multi-bit data packets into a single-bit stream for the transmission over a wireline cable.
Currently, we are designing a serializer adapted to the operating conditions of the ITS3 detector. This version abbreviated as GWT-PSI (Gigabit Wireline Transmitter Power Supply Immune) will run at 10.24Gbps data rate. The ITS3 requires that the GWT-PSI circuit will operate connected to the noisy (chip-level) power supply bus.
To mitigate the power supply noise effect a low-dropout regulator (LDO) circuit has been included in the GWT-PSI block. The LDO circuit is an external-capacitor-less type regulator generating stable and fluctuation-free output voltage to power critical blocks. The LDO provides a -50 dB PSRR (power supply rejection ratio) at low frequency (<1MHz) with the deterioration to a -32dB level at the worst point at the frequency of 110MHz. The LDO consumes only 0.74mW of power.
For reliable operation of a 10.24Gbps serializer a low-time-jitter (rms ≈ 6ps) clock signal is required. No such quality reference clock will be provided in the ITS3. That is why we included a PLL (phase-locked loop) circuit in the GWT-PSI. The PLL (charge pump topology with an RC ring-oscillator VCO) generates a 640MHz clean output clock. The power consumption of the PLL is 1.6mW (1.2V x 1.3mA).
The GWT-PSI consists of a digital core and an analog core. The digital core includes a dual port asynchronous FIFO needed to transfer 32-bit data packets from a 320MHz noisy clock domain into 16-bit output packets to a 640MHz clean clock domain. The output data packet is stored in an 8-bit register driven by the positive edge of the clock and an 8-bit register driven by the negative edge of the clock. In the analog core, a 16-phase round-robin multiplexer is used to transmit the data from the registers to the inputs of the line driver bit-by-bit in an interleaved manner. A multi-phase delay-locked loop (DLL) generates 16 phases evenly spaced (97ps) in the period (1.56ns) of a 640MHz clock. The edge-combiner block converts the phase signals into the selection signals for the multiplexer.
We use a voltage-mode source-series terminated (SST) differential line driver to transmit large swing (±0.6V) signals over a 100Ω cable. The power of the line driver is 7.2mW (6mA x 1.2V)
This work reports on the prototypes submitted in the ER1 production run, which include the analog core block of the GWT-PSI, the PLL circuit and the LDO circuit. A dedicated measurement system has been developed for testing radiation effects on the circuits. The experimental results from the first test might become available at the time of the workshop and will be included.
