Speaker
Description
During the ATLAS phase II upgrade, the tracking system of the ATLAS experiment will be replaced by an all-silicon detector called the inner tracker (ITK) with a pixel detector as the most inner part. The monitoring data of the new system will be aggregated from an on-detector ASIC called Monitoring Of Pixel System (MOPS) and sent to the Detector Control System (DCS) using a new interface called MOPS-HUB.
The hardware implementation and experimental results of the MOPS-HUB will be presented. In addition, mitigation techniques including Single-Event Upset (SEU) and Single-Event Transients (SET) for the new system will be introduced.
Summary (500 words)
The ATLAS experiment will get a new inner tracker (ITk) during the phase II upgrade. The innermost part will be a pixel detector. After the upgrade, the
pixel detector will have 5 times more modules than the present state. The ATLAS pixel detector will use a serial powering scheme to reduce the number of services inside the detector volume, therefore a new Detector Control System (DCS) is being developed at the University of Wuppertal to fulfill the control and monitoring requirements of the new pixel detector. The new DCS has an on-detector ASIC called Monitoring Of Pixel System (MOPS) to monitor the voltages and temperatures of the detector modules and other sub-detector components.\newline
A system integration plan of the MOPS chip that includes powering and communication has been proposed with MOPS-HUB as the central unit. The MOPS-HUB is an FPGA based interface. Its main task is the aggregation of monitoring data between the MOPS chips (installed at the vicinity of the detector modules) and the DCS computer.
Beside that, the MOPS-HUB will monitor information per CAN bus (voltage/current) and send it to the DCS computer as part of the data stream. In addition, it will have a full power control over the connected Controller Area Network (CAN).
\begin{figure}[htp]
\centering
\includegraphics[width=0.85\textwidth]{figs/PhD_Designs.png}
\caption{\label{fig:construction} The complete MOPS-HUB network.}
\end{figure}
The core unit of the MOPS-HUB will be the MOPS-HUB FPGA. The Firmware design of the MOPS-HUB FPGA will allow the communication with the MOPS chips over CAN bus using an integrated CAN controller and a physical layer. In addition, the data aggregated between the MOPS-HUB FPGA and the DCS will go through different stages. First, the MOPS-HUB FPGA will communicate with an Embedded Monitoring and Control Interface (EMCI) through low power differential signals called elinks. Second, the EMCI will serve as a bidirectional channel interface that will transmit the data through a high-speed optical link to an Embedded Monitoring Processor (EMP), which is placed in a non-radiation environment (see Figure~\ref{fig:construction}). The EMP will deliver the data to the DCS by means of an Ethernet connection.
Some special requirements on the design and firmware is also considered (e.g TMR and re-configuration) since MOPS-HUB will be placed in a radiation environment.
The hardware implementation and experimental results of the MOPS-HUB and its integration plan will be presented. In addition, mitigation techniques including Single-Event Upset (SEU) and Single-Event Transients (SET) for the new system will be introduced.
