Speaker
Description
The MicroTCA standard is widely used in the field of particle physics, and Advanced Mezzanine Card is the basic component of the MicroTCA system that requires module management control (MMC) for management. RISC-V is an open source ISA (Instruction Set Architecture) with extensive use. In this paper, we implement the MMC firmware on the MCU with RISC-V architecture. We build a universal standard library that is compatible with both the STM32F1XX and GD32VF1XX series MCU based on ARM and RISC-V architecture respectively. Interrupt response time is tested to compare real-time transaction processing performance of two popular processor architectures.
Summary (500 words)
To manage and control the advanced mezzanine card (AMC) which is the basic component of the MicroTCA system, various MMC solutions have been developed. However, most of these solutions operate in polled mode and use MCUs (Micro Controller Units) based on x86 and ARM processor architectures. In our work, we have implemented an MMC solution based on the RISC-V architecture MCU. We used GigaDevice's GD32VF103 MCU chip and implemented all the necessary functions of MMC based on FreeRTOS. Our implementation shows that the real-time performance is better than the polling method.
We build an universal standard library by referring to STM32 standard peripheral libraries. To verify its compatibility, we used the development platform VScode and PlatformIO to compile and download. The result show that the library is compatible with both the STM32F1XX series MCU and GD32VF1XX series MCU chips based on ARM and RISC-V architecture respectively.
To evaluate the real-time performance of the two chips, we downloaded the FreeRTOS-MMC firmware to both MCUs through the JLink tool and inserted the AMC based on these two chips into the MicroTCA chassis. We performed interrupt response time tests by inserting and unplugging the hot-swappable handle. They have different interrupt response performance.
We analyzed the reasons for this difference by comparing the processor of the ARM architecture (taking Cortex-M3 as an example) and the processor of the RISC-V architecture (taking Bumblebee as an example). The interrupt response mechanism of the two processors is very different. In the ARM Cortex-M processor, the work related to the interrupt response is all done by the hardware. In contrast, in the RISC-V Bumblebee processor, before the processor enters the interrupt service program, the context needs to be saved by the software first, and the complete interrupt response is done by the hardware and software. Additionally, after compiling the source program into assembly instructions, the number of instructions between them is also different, with RISC-V having more instructions than ARM, about 6%
