Speaker
Description
Beam monitor is a sub detector for the CSR external-target experiment (CEE) at HIRFL, which is designed to monitor the beam status. A custom-designed pixel chip Topmetal-CEEv1 acts as the sensor for locating the position of each particle. In this paper, we present a prototype readout system for beam monitor. Injected pulse test and 241Am alpha test in the laboratory as well as beam test at HIRFL has been done to validate the functionality of the system. The results show that the system could control and configure the pixel chips and read out data from the front end electronics.
Summary (500 words)
The Cool Storage Ring (CSR) of the Heavy Ion Research Facility in Lanzhou (HIRFL) is a powerful machine to probe the uncharted nuclear physics field, delivering a variety of heavy ions of element from carbon to uranium and with energies up to 1 GeV/u. The External-target experiment (CEE) at HIRFL-CSR, which is designed to study the nuclear matter phase structure at low temperature and low baryon density, is currently under development. Beam monitor is a sub detector of CEE, which is designed to monitor the beam status. Topmetal-CEEv1, a custom designed pixel chip, acts as direct charge sensor for locating the position of each particle. In order to configure the pixel chips and read data from the front end electronics, a prototype readout system is designed for beam monitor.
The system consists of a bonding board, a front end board and a readout unit. There are four TopmetalCEEv1 chips on top side of the bonding board and they are placed in three rows. With this layout scheme, no dead detection area is left and the effective detection area can reach more than 50 mm to meet the requirements. The front end board is designed to provide the required power, configure TopmetalCEEv1 chip, convert the analog signals, package data and transfer it to back end. As the distance between these two boards and the readout unit (back end) is about 10 meters, a SAMTEC cable is used to transmit power supply and high speed serial signals. Moreover, these two boards are placed inside a magnetic shield in the dipole magnet, the structure and size of the boards, radiation hardening of the devices and cooling are all need to carefully consider. The readout unit is a board based on Xilinx Kintex-7 FPGA. It could receive clock and trigger signals from clock and trigger system. And it could transmit data using transceivers in FPGA with front end board. The interface between the readout unit and the DAQ/PC is the optical fiber/Gigabit Ethernet.
The firmware architecture is divided into physical layer, data link layer, transport layer and application layer. The first three layers are mainly for data stream transmission, while the application layer is mainly for data stream processing. Data stream transmission part is implemented based on Xilinx FPGA transceiver and the widely used high-speed serial communication protocol Aurora 8b/10b. And the transmission protocol between modules is AXI-Stream. For data stream processing part, data stream merging, preprocessing and command distribution are implemented. The standard protocol and interface can effectively increase the independence between layers, reduce the coupling between modules, and make the firmware easy to modify, migrate, and maintain.
The prototype readout system has been designed and the corresponding boards have been produced. Injected pulse test and 241Am alpha test in the laboratory as well as beam test at HIRFL has been done to validate the functionality of the system. The results show that the system could control and configure the pixel chips and read out data from the front end electronics.
