Speaker
Description
The status of the development of the Level-0 endcap muon trigger system for the ATLAS experiment at the HL-LHC is presented. Integrations of the new trigger algorithms and the implementation with firmware on a new prototype of the trigger board (Sector Logic, SL) are also presented. Results from hardware tests of the SL prototype board and integration tests with the newly developed front-end board are also shown.
Summary (500 words)
HL-LHC is planned to start its operations in 2029 with more than 3 times the instantaneous luminosity of the LHC Run 3. To cope with the proton-proton collision rate higher than that of LHC, the trigger and readout system of the ATLAS experiment needs to be replaced. The new Level-0 muon trigger system is required to reconstruct muon candidates with an improved momentum resolution to suppress the trigger rate with keeping the efficiency. That can be achieved by combining the signals from various subdetectors(InnerCoincidence): Resistive Plate Chamber (RPC), Thin Gap Chamber (TGC), New Small Wheel (NSW), Monitored Drift Tube (MDT), and scintillator-steel hadronic calorimeters (TileCal) to form more offline-like tracks.
The Sector Logic (SL) boards play a key role in the new Level-0 muon trigger system. The full system includes 80 SL boards, covering pseudorapidity (eta) range |eta| < 2.4. They receive the hit data of RPCs (barrel, |eta| < 1.05) and TGCs (endcap, 1.05 < |eta| < 2.4) from the on-detector electronics and reconstruct muon candidates. The signals from NSW and TileCal are combined with the information of the muon candidates reconstructed in RPCs and TGCs to suppress fake trigger from non-collision particles. The selected muon candidates are transferred to the boards dedicated to processing of the MDT hits, where further selection is applied with improved momentum resolution. The SL boards also serve as the readout boards of the RPC and TGC hit data.
Each SL board is designed as an ATCA blade, integrated with Virtex UltraScale+ XCVU13P FPGA, Mercury XU5 MPSoC mezzanine card, and CERN-developed IPMC. FireFly modules provide 120 pairs of transmitters and receivers. Clock is managed with Si5345 chips and fixed latency scheme is employed. Power is supported up to 350 W. The first prototype (attachment 1) of the SL board was produced in Oct. 2021. All the functions of the hardware were demonstrated and confirmed after minor modifications from the first prototype. We are finalizing the design according to these results, and also preparing a test environment utilizing the MPSoC on the board.
The trigger firmware is supposed to be implemented on XCVU13P FPGA. Integration of the algorithms for the track segment reconstruction using TGC hits, InnerCoincidence and track selection is accomplished with realistic resource usage of ~40% and acceptable total latency of ~500 ns.
The performance of the trigger algorithms is evaluated with single muon MC samples overlayed with the pile-up events expected in the possible highest luminosity of HL-LHC (µ=200), and also verified with a bit-wise simulator.
