Conveners
ASIC
- Angelo Rivetti (INFN - National Institute for Nuclear Physics)
ASIC
- Ping Gui (Southern Methodist University (US))
ASIC
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
ASIC
- David Gascon (University of Barcelona (ES))
ASIC
- Angelo Rivetti (INFN - National Institute for Nuclear Physics)
ASIC
- Ping Gui (Southern Methodist University (US))
ASIC
- Adriano Lai (Universita e INFN, Cagliari (IT))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
H2GCROC is the 130nm CMOS ASIC designed to read out the SiPMs coupled to the scintillating tiles of the back hadronic sections of CMS HGCAL (High Granularity Calorimeter). Each of its 72 channels is composed of a current conveyor, a high-gain preamplifier, a shaper, and ADC to read the energy, with two discriminators connected to TDCs for time-of-arrival and time-over-threshold information,...
With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65nm CMOS, are radiation tolerant (200 Mrad) with low power consumption (<2.5...
This talk describes the characterisation and validation campaign of the prototype of the CMS Readout Chip (CROC), a 65 nm CMOS pixel readout ASIC for the CMS Inner Tracker upgrade for High Luminosity LHC. This validation campaign includes tests with single-chip and multi-chip modules, irradiation campaigns, test beams and wafer-level tests. The main results obtained in the testing of the CROC...
The RD53 Collaboration, established in 2013 as a joint effort between ATLAS and CMS pixel ASIC communities on 65nm CMOS technology, is now in the phase of implementing final pixel readout chips, referred to as RD53C revisions, that will be used into upgraded pixel detectors at HL-LHC. The purpose of this work is to provide a comprehensive review of most important architectural design choices,...
The COLUTA ASIC is an 8-channel 15-bit 40 MSPS ADC fabricated in 65 nm CMOS for the upgrade of the readout of the ATLAS LAr calorimeter for the high luminosity LHC. The ADC architecture couples a 3.5-bit Multiplying-DAC (MDAC) stage to a successive approximation register (SAR) ADC with a digital back-end that outputs sample data continuously via 640 Mbps serial LVDS. The analog performance and...
The LHC upgrade requires redoing the LAr calibration system which should provide a 16-bit range signal with 1‰ accuracy while being radiation tolerant. The former operating principle is used: a precise current is stored in an inductor, when it is switched off, a pulse is generated to be injected in the readout electronics. This is achieved by two chips: the first one, in TSMC 130nm, provides...
The MOSS (Monolithic Stitched Sensor) chip is a
monolithic pixel prototype chip measuring (\qty{25.9}{cm}\times\qty{1.4
}{cm}). It was designed to explore the stitching technique,
to investigate the achievable yield and as a proof of concepts for
the sensors for the ALICE ITS3 upgrade. It was manufactured in
early 2023.
This submission will focus on the MOSS chip and on its...
During the next LHC Long Shutdown, the innermost three layers of the ALICE Inner Tracking System will be replaced by a new vertex detector composed of curved ultra-thin monolithic silicon sensors. The R&D initiative on monolithic sensors of the CERN Experimental Physics Department, in synergy with ALICE ITS3 upgrade project, prepared the first submission of chip designs in the TPSCo 65 nm...
ALFE2 is an ATLAS Liquid Argon Calorimeter (LAr) Front-End ASIC designed for the HL-LHC upgrade. ALFE2 comprises four channels of pre-amplifiers and CR-(RC)2 shapers with adjustable input impedance. ALFE2 features two separate gain outputs to provide 16-bit dynamic-range coverage and an optimum resolution for small signals. ALFE2 is characterized using a Front-End Test Board (FETB) based on a...
4D tracking with ~10ps timing is crucial for reducing the combinatorial challenge of track reconstruction at high pileup densities, it offers completely new handles to detect and trigger on LLP and enables particle-ID capabilities at low transverse momentum. At the Muon Collider, the timing information will be essential for reduction of BIB. A high-precision TDC is a critical block necessary...
The IGNITE project is developing solutions for the next generation of trackers at colliders. It plans to implement an integrated system module, comprising sensor, electronics, and fast readout, aimed at 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In the present paper we present recent advancements on the design of a prototype ASIC,...
The CMOS Monolithic Active Pixel Sensor MIMOSIS being developed for the CBM experiment at FAIR will combine a spatial resolution of 5 µm with a time stamp of 5 µs and operate at peak rates of 80 MHz/cm². The full-scale prototype MIMOSIS-1 met these specifications , and the recently submitted MIMOSIS-2 has addressed shortcomings identified during the dense test campaign. Both complex...
We present a new kind of sensors made of 5µm pixels using 6-metal TJ 180 nm technology. The pixels are interconnected among themselves to conducting lines with three directions 0°, 120° and -120°. Two neighbouring pixels are connected to different lines with different directions. The lines are connected to readout cells hosting current amplifier with its current comparator, together with the...
An HV-CMOS (High-Voltage CMOS) prototype detector for particle detection in high energy physics experiments, named UKRI-MPW0, has been developed. This chip implements a novel sensor cross-section optimised for biasing the chip from the backside only and achieves an unprecedented breakdown voltage (> 600 V). With such a high breakdown voltage, UKRI-MPW0 is expected to achieve much improved...
Targeting on low power consumption and high spatial resolution, the CPV-4 SOI pixel sensor requires about 100 transistors to implement the analog-digital mixed circuit functionality within a given pixel area around 16 um x 20 um. By utilizing 3D vertical integration, signal amplification and threshold discrimination are achieved in the lower-level circuitry, while hit information storage and...
NAPA-p1 is a prototype Monolithic Active Pixel Sensor designed in 65 nm CMOS imaging technology, developed to meet requirements for future e+e- colliders. The prototype has dimensions of 1.5 mm × 1.5 mm with a pixel pitch of 25 μm. In nominal conditions, simulations show a pixel jitter of 350 ps-rms and an Equivalent Noise Charge (ENC) of 12 e-rms. The prototype will be characterized this...
This paper reports the design and measurement results of a 768-channel of 14-bit analog to digital converters. Each channel’s layout pitch is only 8.5µm with a sampling rate from 40KS/s up to 100KS/s. Testing results show a crosstalk about only +/- 1 LSB. The architecture of the circuit and the structure of the layout make it extensible to exceptionally large format of detectors beyond 1000...
The paper presents a Dual Use Driver (DUDE) that is a component designed for the “Demonstrator ASIC for Radiation-Tolerant Transmitter” in 28nm (DART28) and is developed in R&D programme on technologies for future experiments. The driver operates at 25.6Gbps and it allows to drive either 100Ω transmission lines and optical ring modulators in a Photonics Integrated Circuit. The driver includes...
We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase-Locked Loop under a 63 MeV proton beam of instantaneous fluence 10^10 protons/cm²/s. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) for the High-Luminosity Large Hadron Collider (HL-LHC). Observed...
This work introduces AI-In-Pixel-65, an ROIC test chip designed for pixelated X-ray detectors using a 65nm Low Power CMOS process. The study compares two data compression techniques, Principal Component Analysis (PCA) and AutoEncoder (AE), implemented within the chip's pixelated area to address I/O bottlenecks. Our design methodology utilizes high-level synthesis (HLS) and hls4ml, offering...
The combination of 3D tracking and high-precision timing measurements has been identified by the European Committee for Future Accelerators as a fundamental requirement to increase detection capabilities for future applications. Among others, on-chip high-quality clock is a key factor determining the overall resolution of Timing ASICs. However, in large and dense chips, power-grid drops can...
