Conveners
Programmable Logic, Design and Verification Tools and Methods
- Johan Alme (University of Bergen (NO))
Programmable Logic, Design and Verification Tools and Methods
- Alex Kluge (CERN)
Programmable Logic, Design and Verification Tools and Methods
- Johan Alme (University of Bergen (NO))
FLX-182 is a PCIe card designed for the readout system of the ATLAS experiment for the High Luminosity phase of LHC starting in 2029. FLX-182 is responsible for decoding and transferring data from the front-ends into the host server memory, and receiving and distributing timing, trigger and control information. About six hundred FLX-182 will sustain 4.6 TB/s of total throughput at 1 MHz data...
As part of the CMS Phase-2 upgrade, a prototype of the receiver of raw trigger data from the HGCAL endcap has been implemented using the Serenity ATCA platform. The receiver firmware was developed to test the unpacking of data from the front-end endcap trigger concentrator ASIC and measure its performance and stability. The firmware mainly consisted of unpacker blocks to decode ASIC packets,...
Several physics experiments are moving towards new acquisition models. In this work implementation of Remote Direct Memory Access (RDMA) directly on the front-end electronics has been explored, in this way is possible to free part of the computing farm's CPU resources. The work also introduces new verification techniques for verifying RDMA over Converged Ethernet (RoCE) firmware block...
The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications.
This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the...
ALTIROC3 is the second version of the ASIC for the ATLAS High Granularity Timing Detector to read out full size LGAD sensors (15x15 pixels of 1.3mm x 1.3mm). The ASIC, designed in 130nm technology, comprises around 250k flip-flops, more than 1000 8-bit configuration registers, and several clock domains and implements different analog IP-blocks critical for digital data acquisition and...
The ALICE collaboration is developing the new Inner Tracker System 3 (ITS3), a novel detector that exploits the stitching technique to construct single-die monolithic pixel sensors of up-to 266 mm x 93 mm. ITS3 requires all hits from a particle flux of 4.4 MHz/cm2 to be transmitted on-chip to one of the sensor edges. This on-chip readout is limited by a power budget of 20 mW/cm2, a readout...
An increasing interest is growing towards reconfigurable processing systems embedded on the detector ASICs. Explorative work has been carried out to investigate Single-Event Upset (SEU) rates in open source RISC-V processors. The Ibex RISC-V core includes hardware security features that could detect SEUs in the core and alert the System-on-Chip (SoC) for possible malfunctions. This research...
The use of a radiation-hard microprocessor or the application of a System-on-Chip (SoC) design methodology has a considerable beneficial impact on the future design of ASICs within the HEP community. The STRV (SEU-tolerant-RISC-V) is a Triple Modular Redundancy (TMR) protected RSIC-V microprocessor designed to withstand Single Event Effects (SEE) and operate close to a beamline or interaction...
In the ALICE read-out and trigger system, the present GBT and CRU based solution will also serve for Run4 without major modifications. By now, the GBT protocol has been superseded by lpGBT, and the GBT ASIC is not available for new productions. Extensions of the ALICE system (e.g. the planned FoCal detector) will therefore require to use lpGBT while keeping the compatibility with the existing...
