Speaker
Description
For the upcoming HL-LHC upgrade of the ATLAS experiment, the deployment of GPU
or FPGA co-processors within the online Event Filter system is being studied as
a measure to increase throughput and save power. End-to-end track
reconstruction pipelines are currently being developed using commercially
available FPGA accelerator cards. These utilize FPGA base partitions, drivers
and runtime tools supplied by the manufacturer to reduce design effort.
Algorithms are implemented both in hardware description language (HDL) and
high-level synthesis (HLS), and integrated as kernels into an OpenCL host
software interfacing with the ATLAS main software framework Athena. This
contribution summarizes the algorithmic developments, the integration workflow
and status.
