Speaker
ATLAS Collaboration
Description
The design and status are reported for the development of the Level-0 muon trigger hardware of the ATLAS experiment at HL-LHC. The hardware is designed as an ATCA blade, integrating a Virtex UltraScale+ XCVU13P FPGA, a Mercury XU5 MPSoC mezzanine card, and a CERN-developed IPMC. The FireFly modules provide 120 transmitter and receiver pairs. The clock is managed by a Si5395 chip and employs a fixed delay scheme. Power is supported up to 350 W. The final prototype was produced in 2024 and all the functions of the hardware were demonstrated and confirmed.
Authors
ATLAS Collaboration
Borut Paul Kersevan
(Jozef Stefan Institute (SI))
