Speaker
Description
Developments in microprocessor technology have confirmed the trend towards higher core-counts and decreased amount of memory per core, resulting in major improvements in power efficiency for a given level of performance. Per node core-counts have increased significantly over the past five years for the x86_64 architecture, which is dominating in the LHC computing environment, and the higher core density is not only a feature of large HPC systems, but is also readily available on commodity hardware preferentially used at Grid sites. The baseline multi-core workloads are however still largely based on 8 cores, and the LHC experiments employ different strategies for scheduling their payloads at sites. In this work we investigate possible implications of scaling up core-counts for grid jobs, up to whole node where possible.
| Desired slot length | 15 minutes |
|---|---|
| Speaker release | Yes |
