Conveners
ASIC
- Christophe De La Taille (OMEGA (FR))
ASIC
- Christophe De La Taille (OMEGA (FR))
ASIC
- Alex Grillo (University of California,Santa Cruz (US))
ASIC
- Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
ASIC
- Marcus Julian French (STFC - Rutherford Appleton Lab. (GB))
ASIC
- Alex Grillo (University of California,Santa Cruz (US))
ASIC
- Jean-Pierre Cachemiche (Centre National de la Recherche Scientifique (FR))
The ATLAS experiment will use an all-silicon tracker in the Phase II upgrade for the HL-LHC collider at CERN. For the Silicon Strip detector of the ITk, a new readout chip ABCStar is under design to meet the new requirements of higher trigger rates and lower latency. We summarize the status of this work and present the new features of the chip.
SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Tracker of LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit...
PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. It will be composed of four barrels and six disks, instrumented with silicon hybrid pixel detectors and double-sided microstrip detectors.
PASTA (PAnda STrip ASIC) is the readout chip for strip sensors.
An overview of the chip, of its readout system and of...
This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64x64 matrix of 50x50$\mu m^2$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5 % at 3GHz/cm$^2$ pixel rate, 1MHz trigger with 12.5$\mu$sec latency. Two analog front end designs, one synchronous and one asynchronous, are...
This work describes the design, in 65nm CMOS, of a very compact, low power, low threshold synchronous analog front-end for pixel detectors at HL-LHC. Threshold trimming is avoided using offset compensation techniques. Fast ToT encoding is possible, as the comparator can be turned into a Local Oscillator up to few hundreds MHz. Two small prototypes have been submitted and tested; a X-ray...
ICPIX28 is the first 28nm bulk-CMOS readout frontend for High Energy Physics pixel detectors. It performs the conversion of the input charge into a voltage signal, hence detect the charge arrival time and amount of charge information through Time-over-Threshold signal. The front-end is composed by the cascade of a Charge Sensitive Preamplifier and a low-power switched-capacitor...
HEPS-BPIX is a dedicated hybrid pixel detector for the High Energy Photon Source in China. It works in the single photon counting mode, and each pixel chip contains an array of 10472 pixels with a pixel size of 150um150um. Based on the successful design of the chip, the detector module was assembled by bump bonding with 2*4 pixel chips and a single large sensor. Six detector modules were...
We have been developing a monolithic type pixel detector for the ILC vertex detector with 0.2 um fully depleted SOI CMOS process. We are aiming to achieve 3 um of a single point resolution that is required for the ILC with a 20 um x 20 um pixel. Beam test result of the first prototype sensor that an amplifier and an analog memory are implemented in each pixel is presented. Design of second...
This paper presents the SAMPA, a new ASIC for the ALICE upgrade for Time Projection chamber (TPC) and Muon chamber (MCH) read-out frontend electronics.
The SAMPA ASIC is designed in 130nm CMOS technology with 1.2V nominal power supply. SAMPA includes 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel comprises a Charge...
SKIROC2_CMS is a chip derived from CALICE SKIROC2, providing 64 channels of low noise readout for 50pF Si-sensors over 10pC dynamic range. The pre-amps are followed by high/low gain 25ns shapers, 16-deep 40 MHz analog memory “waveform sampler” and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA...
HARDROC is the very front end chip designed to readout the Resistive Plate Chambers foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the calorimeter implies thousands of electronics channels per cubic meter which is a new feature of “imaging” calorimetry. Moreover, for compactness, chips must be embedded inside the...
Petiroc2a is a 32-channel front-end ASIC designed in AMS 0.35µm SiGe technology to read out Silicon Photomultipliers (SiPMs) for applications requiring accurate time resolution and energy measurement over a large dynamic range.
Each channel integrates a 20GHz Gain Bandwidth preamplifier followed by an ultra fast discriminator and a TDC. The first incident photons can be measured with a time...
The TOFPET2 ASIC is a low-power, low-noise, readout and digitization chip for SiPMs sensors implemented in 110nm CMOS technology optimized for time-of-flight measurements. The circuit has 64 independent channels including quad-buffered TDCs and charge integration ADCs in each channel, and is an evolution of the TOFPET1 ASIC, which was developed in 130nm CMOS technology for Positron Emission...
The design and measurement results of four ultra-low power 10-bit SAR ADCs, fabricated in CMOS 130~nm technology, are presented. All prototypes use very similar architecture with main difference in split in the capacitive DAC network. The prototypes are fully functional, achieve excellent linearity (DNL < 0.3 LSB and INL ~0.5 LSB), and show very good ENOB above 9.5 for 0.2 Nyquist input...
This paper presents a 4-chanel TDC chip demonstrator with the following features: 15-ps resolution, 1280 ns dynamic range, dead time < 20 ns, up to 10 MHz of sustained input rate per channel, around 60 mW of power consumption and very low area in a 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry which is based on a resistive...
We present designs and test results of two ASICs, VLAD and lpVLAD. Each is a 4-channel, 10-Gbps-per-channel VCSEL array driver fabricated in a 65 nm CMOS technology. lpVLAD deploys a novel high-efficient output structure to achieve a record low power consumption of 25 mW/ch when delivering 2 mA bias and 6 mA modulation currents at 10-Gbps. Eye diagrams of both two designs under post-layout...
The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 um process from TowerJazz. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process.
The DTU...
