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Description
Summary
The signal amplification and summation electronics of the ATLAS Hadronic End-cap Calorimeter
(HEC) is operated in liquid argon at the circumference of the HEC calorimeters inside the cryostats.
The present electronics is designed to operate at irradiation levels expected for the LHC. For
operation at the sLHC the irradiation levels are expected to be a factor 10 higher, therefore a new
electronic system will be needed. The technological possibilities are investigated.
The basic element of the cold HEC electronics is an integrated chip consisting of eight
preamplifiers and two summing amplifiers. The concept of 'active pads' is employed, i.e. each
preamplifier is connected to one pad of the calorimeter cells, the individual signals being amplified.
The read-out channels are formed by summing signals from 2/4/8 or 16 pads to the required output
granularity with subsequent amplification. This concept results in an optimal signal to noise ratio.
The HEC electronics has to fulfil two stringent requirements: It has to operate in liquid argon (~87
K) and it has to operate reliably in the radiation levels of the end-cap calorimeter region.
There are more detailed requirements, among those:
• The power consumption of the chip should not exceed the present level of < 0.2 W in order to
avoid boiling of LAr;
• the gain difference between individual preamplifier channels of one IC has to stay below 1%
since the electronic calibration is done at the level of the summed read-out channel;
• the gain difference of a read-out channel between operation in warm and cold should not be
more than a factor of 2 since most QC tests have to be done in warm;
• the noise level should not exceed the present low level;
• the dynamic range of the preamplifier has to be 12-bit, that of the summing amplifier 13-bit;
• the IC has to be safe with respect to potential HV discharges in the gaps of the HEC. April 2-3,
From irradiation tests of the present HEC electronics it is known that it will operate up to a dose of
55 kGy of ionizing radiation and up to a neutron fluence of 3 * 1014 n/cm2, where it shows
some degradation of performance. This is about a factor of 20 above the expected neutron fluence
of 1.5 * 1013 n/cm2 for an operation of 10 years at LHC. It will take at least one year of LHC
operation at a sizeable luminosity to determine the irradiation levels in situ. Therefore, presently a
safety factor of 10 has been assumed to take all systematic uncertainties into account. Within this
safety factor, the present electronics matches well the LHC requirements. For 10 years of sLHC
operation at a luminosity of 1035 /cm2/s the chips have to survive ten times higher radiation
levels: γ dose 50 kGy, 1.5·1014 n/cm2, 1.2·1012 p/cm2. A new radiation hard HEC
electronics will be needed.
Therefore generic studies of different technologies have been carried out at the transistor level to
understand the radiation hardness up to integrated neutron fluxes of ~21016 n/cm*2 and the
behaviour during operation at cryogenic temperatures.
The following technologies have been studied: Bipolar SiGe (IHP 250 nm, IBM 130 nm, AMS 130
nm, Sirenza), CMOS Si (IHP 250 nm n and p), GaAs MESFET and HEMT (Triquint 250 nm,
Sirenza 250 nm). The S-parameter technique has been used to monitor the performance e.g. of gain
and linearity during irradiation at room temperature. In addition, DC measurements before and after
irradiation have been compared. Results of these tests and of accompanying noise tests are reported.
In addition, results of S-parameter measurements will be reported operating the transistors in liquid
nitrogen. The dynamic range requirements pose a scrutinizing test on the technologies.
Conclusions are drawn and the potential is assessed on the viability of using the tested technologies
for carrying out the design of new HEC cold electronics for the sLHC.
