Speaker
Ernesto PEREA
Description
The seminar addresses recent advances in CMOS
technologies. Technological limits, device-related limits
and fundamental physical limits linked to the diminished
feature sizes and their impact on analog performance
and digital integration potential are discussed. Progress
is made in new semiconductor/dielectric materials and
in band-gap engineering to overcome some of the
unfavorable effects at the microscopic/quantum level.
Overall system cost pressures call for improved
fabrication yields, forcing new tightly-coupled system-
architecture-circuit-device design techniques in a
context of ever increasing parameter variability. A
detailed account of current device architectures beyond
45nm including performance boosters will be presented
together with their associated advantages and risk
factors. New paradigms will be necessary to reduce the
analog-digital divide. One possible approach is the use
of long-time known sampling techniques for Analog and
RF circuits, opening the way to fully integrated
reconfigurable systems, a concept that has been
around for many years, but that is regaining interest.
