Sep 25 – 29, 2006
Valencia, Spain
Europe/Zurich timezone

CMOS directions in industry

Sep 25, 2006, 4:30 PM
45m
Valencia, Spain

Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN

Speaker

Ernesto PEREA

Description

The seminar addresses recent advances in CMOS technologies. Technological limits, device-related limits and fundamental physical limits linked to the diminished feature sizes and their impact on analog performance and digital integration potential are discussed. Progress is made in new semiconductor/dielectric materials and in band-gap engineering to overcome some of the unfavorable effects at the microscopic/quantum level. Overall system cost pressures call for improved fabrication yields, forcing new tightly-coupled system- architecture-circuit-device design techniques in a context of ever increasing parameter variability. A detailed account of current device architectures beyond 45nm including performance boosters will be presented together with their associated advantages and risk factors. New paradigms will be necessary to reduce the analog-digital divide. One possible approach is the use of long-time known sampling techniques for Analog and RF circuits, opening the way to fully integrated reconfigurable systems, a concept that has been around for many years, but that is regaining interest.

Primary author

Presentation materials