The GERDA experiment under construction at the Gran Sasso Laboratory is
searching for neutrinoless double beta decay of 76Ge. Germanium diodes immersed
in liquid nitrogen serve as sources and detectors. Since the detectors are
operated in an unprecedented low background environment the amplifiers, which
are operated close to the diodes in liquid nitrogen, have to fulfil stringent
requirements on low radioactivity, noise performance and be able to drive the
signal off detector. The F-CSA104 has been designed to fulfil these
requirements by an appropriate technology choice and optimised architecture.
The F-CSA104 has been fabricated in the XFAB 0.6 um CMOS process as it offers a
large signal output voltage swing (5V operation voltage), bulk-effect-less(i.e.
substrate isolated) NMOS FET devices and no noticeable noise penalty over XFAB's
0.35um CMOS technology. For the low operating temperature of -196°C the
simulation’s temperature was matched to the measured device characteristics.
For the GERDA experiment it is desirable to have a completely integrated circuit
so as not to degrade the radio-purity of the liquid nitrogen vessel. In
particular, integrating the large feedback resistor of the CSA. However,
integrating such a large resistor required the use of a substrate isolated NMOS
FET operating in the sub-threshold region. Special electronic circuitry and
layout has been used to allow the NMOS FET resistor to work in both signal input
polarities and to maintain a reasonably accurate and stable resistance.
The F-CSA104's noise performance has been optimized for use with capacitive
detectors of 1 - 100pF. Measurements have shown that a PMOS input transistor
suffered less flicker noise than an NMOS; Flicker noise being the dominant noise
contributor at liquid nitrogen temperatures for optimal filter constants. To
minimise the thermal noise, a large width over length PMOS input transistor
channel of 9000/0.6 has been implemented. Layout techniques for this transistor
have been used to reduce the stray capacitance and to screen the input line from
bulk noise. So as the F-CSA104 may find use in other applications where the
noise matching to higher capacitance detectors is vital, an external PMOS FET
may be connected to the IC and thus operates in place of the integrated input
A range of F-CSA104's parameters, including offset and preamplifier decay
constant, can be programmed by I2C commands for optimisation. Further to this,
several options exist to select various reference points for sensitive nodes.
An example of this would be the bulk node of the input transistor which can be
selected to be either supplied externally (to further reduce bulk resistance
noise) or be on chip ground.
F-CSA104's linearity and offset have been designed for use with 14 bit ADC
systems. Linearity requires a large open loop gain of both preamplifier and
buffer core cells (120 db and 92 db, respectively). This large open loop gain
also minimises signal-induced input voltage shifts (max. 0.44 uV) and thus
minimises charge collection deficit. Offset cancellation is achieved by a triple
DC offset suppression scheme.
The F-CSA104’s measured power consumption, noise, S/N and signal output rise and
fall times are presented for both room and liquid nitrogen operating
temperatures. Other measurements of interest are also presented such as the
power supply rejection ratio, channel cross-talk and common mode rejection