Sep 25 – 29, 2006
Valencia, Spain
Europe/Zurich timezone

Readout Electronics Tests and Integration of the ATLAS Semiconductor Tracker

Sep 26, 2006, 4:45 PM
25m
Valencia, Spain

Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN

Speaker

Vasiliki Mitsou (Instituto de Fisica Corpuscular (IFIC) UV-CSIC)

Description

The SemiConductor Tracker (SCT) together with the pixel detector and the Transition Radiation Tracker (TRT) form the central tracking system of the ATLAS experiment at the LHC. It consists of single-sided microstrip silicon sensors, which are read out via binary ASICs based on the DMILL technology and the data are transmitted via optical fibres. After an overview of the SCT detector layout and tracking performance, the final-stage assembly in large-scale structures and the integration with the TRT is presented. The focus is on the electrical performance of the overall SCT detector system through the different integration stages, including the detector control and data acquisition system.

Summary

The ATLAS Semiconductor Tracker (SCT) will be a central part of the tracking system
of the ATLAS experiment and is one of the major new silicon detector systems for LHC.
The final system comprises about 4000 individual detector modules with nearly 16000
silicon sensors and more than 6 million readout channels. It has been assembled and
is currently being tested as part of the ATLAS Inner Detector Integration effort at
LHC point 1. The testing of the readout and control systems constitutes one of the
vital tasks for the assembled detectors.

The SCT readout system is based on the ABCD3TA, a binary ASIC designed in the DMILL
technology. Each module is read out by 12 ABCD3TA ASICs mounted on a hybrid circuit.
Each chip provides binary readout of 128 detector channels. The amplified and shaped
input signal is compared to a programmable threshold having two components: a single
8-bit DAC applied across the whole chip, and a channel-specific 4-bit DAC designed to
compensate for channel-to-channel variations. In ATLAS, an optical scheme will be
used to transmit data from the detector modules to the off-detector electronics and
to distribute Timing, Trigger and Control (TTC) data from the counting room to the
front-end electronics. The performance of the whole chain of data and control
transmission is verified in each step of the detector assembly.

After a brief overview of the SCT detector system and its expected tracking
performance, the presentation will focus on the system integration of the SCT and in
particular in the installation and testing of the readout system. The final stage
assembly of the SCT and the final integration with the Transition Radiation Tracker
(TRT) is carried out in the ATLAS SR1 clean-room. Using a silicon test system, which
can characterize up to one million readout channels simultaneously, the SCT detector
function and performance is tested through the different integration stages, from
single barrels up to the final tests as part of the Inner Detector (ID) just before
its installation in the pit. Particular attention will be given to the electronics
tests results such as electrical connections checks, noise and gain measurements, as
well as temperature and leakage current measurements. The outcome of these tests is
essential for the validation of the grounding, shielding and cooling system. The
detector control system installation will be highlighted as well.

Primary author

Vasiliki Mitsou (Instituto de Fisica Corpuscular (IFIC) UV-CSIC)

Presentation materials