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TWEPP 2017 Topical Workshop on Electronics for Particle Physics

11–15 Sept 2017
US/Pacific timezone

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Session

TUTORIAL

15 Sept 2017, 09:30

Conveners

TUTORIAL: ASIC Design below 65 nm: Benefits and Challenges with Designing in Advanced CMOS Nodes

  • Alessandro Marchioro (CERN)

Presentation materials

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  1. 192. Advance Node Impact on Physical Design and Resulting Tool Support - Electrically Aware Design Flow
    Sravasti Nair (Cadence Design Systems)
    15/09/2017, 09:30
    Oral
    • New devices (FinFETs) and fluid guardrings
    • Double/ Multiple Patterning aka coloring
    • Gridded/ track based placement and routing methodology
    • In-design dynamic/ post-edit DRC checking to support new constraints including color and grid checks

    Abstract

    Continuous advancement in process technology following Moore’s law over the past few decades has greatly increased IC design...

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  2. 194. Designing CMOS Chips Beyond 65 nm
    Ping Chen (Cadence Design Systems)
    15/09/2017, 11:15
    Oral

    Moore's Law has entered a new frontier as device scaling continues to excel in 10nm and beyond. As the physical dimension of devices and interconnect are being shrunk, the design rules and the design flow, for both design community and EDA community, face unprecedented complexity. Conventional design optimization techniques also need to take the novel process technologies, such as multi-gate...

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  3. 193. 2. Electrically Aware Design Flow
    Sravasti Nair (Cadence Design Systems)
    Oral
    • In-design extraction and analysis of parasitics, EM/ IR and LDE parameters
    • Resimulation with parasitics and LDE parameters from a layout in-progress (prior to sign-off)
    • Using electrical constraints to verify and meet design requirements

    Abstract

    Advanced nodes have introduced many new design challenges including significantly greater impact of parasitics and other electrical...

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  4. 195. Advanced Integrated Simulation Environment
    Ping Chen (Sr. Staff Application Engineer Custom IC & Simulation - Cadence Design Systems)
    Oral

    a. Why we need integrated simulation environment?
    b. Environment for individual block
    c. Environment for block integration.
    d. Environment for verification and regression.
    e. Summary

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  5. 196. System Integration: Integrated IC/Package/PCB Together
    Ping Chen (Sr. Staff Application Engineer Custom IC & Simulation - Cadence Design Systems)
    Oral

    a. Implementation flow
    b. Analysis flow

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