Skip to main content
11–15 Sept 2017
US/Pacific timezone

Session

TUTORIAL

15 Sept 2017, 09:30

Conveners

TUTORIAL: ASIC Design below 65 nm: Benefits and Challenges with Designing in Advanced CMOS Nodes

  • Alessandro Marchioro (CERN)

Presentation materials

There are no materials yet.
Previous tabNext tab
Print
PDF
Full screen
Detailed view
Filter
09:00
10:00
11:00
12:00
Sravasti Nair
Advance Node Impact on Physical Design and Resulting Tool Support - Electrically Aware Design Flow
Earth & Marine Sciences (E&MS) Building, UCSC
09:30 - 11:00
Ping Chen
Designing CMOS Chips Beyond 65 nm
Earth & Marine Sciences (E&MS) Building, UCSC
11:15 - 12:45