Conveners
TUTORIAL: ASIC Design below 65 nm: Benefits and Challenges with Designing in Advanced CMOS Nodes
- Alessandro Marchioro (CERN)
- New devices (FinFETs) and fluid guardrings
- Double/ Multiple Patterning aka coloring
- Gridded/ track based placement and routing methodology
- In-design dynamic/ post-edit DRC checking to support new constraints including color and grid checks
Abstract
Continuous advancement in process technology following Moore’s law over the past few decades has greatly increased IC design...
Moore's Law has entered a new frontier as device scaling continues to excel in 10nm and beyond. As the physical dimension of devices and interconnect are being shrunk, the design rules and the design flow, for both design community and EDA community, face unprecedented complexity. Conventional design optimization techniques also need to take the novel process technologies, such as multi-gate...
- In-design extraction and analysis of parasitics, EM/ IR and LDE parameters
- Resimulation with parasitics and LDE parameters from a layout in-progress (prior to sign-off)
- Using electrical constraints to verify and meet design requirements
Abstract
Advanced nodes have introduced many new design challenges including significantly greater impact of parasitics and other electrical...
a. Why we need integrated simulation environment?
b. Environment for individual block
c. Environment for block integration.
d. Environment for verification and regression.
e. Summary
a. Implementation flow
b. Analysis flow
