Speaker
Tianyang Wang
(University of Bonn (DE))
Description
In order to satisfy the high output bandwidth requirement imposed by the HL-LHC, a high speed transmitter circuit was designed and integrated into the RD53A demonstrator chip for the HL-LHC pixel detector. A CDR/PLL circuit recovers clock from the 160 Mbps incoming data, and provides high speed clock to the serializer, where the 1.28 Gbps output stream is formed. The output stage employs a three-tap current-mode logic driver with adjustable tap coefficient for optimal pre-emphasis. Each RD53A chip includes four output lanes, offering in total 5.12 Gbps output bandwidth. The circuit topology as well as measurement results will be presented.
Authors
Tianyang Wang
(University of Bonn (DE))
Hemperek T.
F. Hügging
H. Krüger
K. Moustakas
P. Rymaszewski
M. Vogt
N. Wermes
