Nov 4 – 8, 2019
Adelaide Convention Centre
Australia/Adelaide timezone

A novel centralized slow control and board management solution for ATCA blades based on the Zynq Ultrascale+ System-on-Chip

Nov 4, 2019, 11:00 AM
15m
Riverbank R5 (Adelaide Convention Centre)

Riverbank R5

Adelaide Convention Centre

Oral Track 1 – Online and Real-time Computing Track 1 – Online and Real-time Computing

Speaker

Oliver Sander (KIT - Karlsruhe Institute of Technology (DE))

Description

Data acquisition systems (DAQ) for high energy physics experiments utilize complex FPGAs to handle unprecedented high data rates. This is especially true in the first stages of the processing chain. Developing and commissioning these systems becomes more complex as additional processing intelligence is placed closer to the detector, in a distributed way directly on the ATCA blades, in the other hand, sophisticated slow control is as well desirable. In this contribution, we introduce a novel solution for ATCA based systems, which combines the IPMI, a Linux based slow-control software, and an FPGA for custom slow-control tasks in one single Zynq Ultrascale+ (US+) System-on-Chip (SoC) module.

The Zynq US+ SoC provides FPGA logic, high-performance ARM-A53 multi-core processors and two ARM-R5 real-time capable processors. The ARM-R5 cores are used to implement the IPMI/IPMC functionality and communicate via backplane with the shelf manager at power-up. The ARM-R5 are also connected to the power supply (via PMBus), to voltage and current monitors, to clock generators and jitter cleaners (via I2C, SPI). Once full power is enabled from the crate, a Linux based operating system starts on the ARM-A53 cores. The FPGA is used to implement some of the low-level interfaces, including IPBus, or glue-logic. The SoC is the central entry point to the main FPGAs on the motherboard via IPMB and TCP/IP based network interfaces. The communication between the Zynq US+ SoC and the main FPGAs uses the AXI chip-to-chip protocol via MGT pairs keeping infrastructure requirements in the main FPGAs to a minimum.

Consider for promotion Yes

Primary authors

Oliver Sander (KIT - Karlsruhe Institute of Technology (DE)) Luis Ardila (KIT-IPE) Mr Denis Tcherniakhovski (KIT - Karlsruhe Institute of Technology (DE)) Matthias Norbert Balzer (KIT - Karlsruhe Institute of Technology (DE)) Marc Weber (KIT - Karlsruhe Institute of Technology (DE))

Presentation materials