Conveners
POSTERS Session
- Mitch Newcomer (University of Pennsylvania)
Dr
Eisse Mensink
(Bruco Integrated Circuits B.V.)
23/09/2010, 16:00
ASICs
Poster
Pixel chips generate a large amount of data. In the foreseen application, the data has to be transported off chip via a micro twisted-pair cable. Because of the low bandwidth of the cable, equalization is needed. Pulse-width modulation turns out to be the best equalization method at the transmitter side. However, at 10Gb/s the eye-opening at the receiver side is very sensitive to the exact...
Tiankuan Liu
(Department of Physics-Southern Methodist University (SMU))
23/09/2010, 16:00
ASICs
Poster
An LC phase locked loop ASIC, fabricated in a commercial 0.25-µm Silicon-on-Sapphire CMOS technology, has been characterized in lab. Random jitter and deterministic jitter are less than 2.5 ps and 10 ps, respectively. The power consumption at 4.9 GHz is 218 mW. The measured tuning range, from 4.7 to 5.0 GHz, is narrower than the simulated values of from 3.8 to 5.0 GHz. The narrow tuning range...
Mr
Sander Heuvelmans
(Bruco Integrated Circuits B.V.)
23/09/2010, 16:00
ASICs
Poster
Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will also be changed; all hit data will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on...
Mr
Patrick Pangaud
(Centre de Physique des Particules de Marseille (CPPM))
23/09/2010, 16:00
ASICs
Poster
Hybrid pixels detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness are currently used in vertex detectors for High Energy Physic experiments. As technology shrinking reaches some limitations, a way to face challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D technologies. This talk presents the design and test...
Mr
Daniel Paer Erik Eriksson
(Department of Physics-Stockholm University)
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
The ATLAS TileCalorimeter contains some 2000 digitizer boards with 2 TileDMU ASICs on each board. Although we have the agreed number of spares this paper discusses a backup version of the digitizer to be used in case more units are required. The TileDMU has been replaced with a cheap and readily available FPGA (Spartan 6) and we have replaced some components to protect against obsolescence....
Mr
Alan Prosser
(Fermilab)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
A collaboration between Fermilab and the Institute for High Energy Physics (IHEP), Beijing has developed a test beam telescope for the IHEP test beam facility. This telescope is based on 5 stations of silicon strips detectors with a pitch of 60 microns. The total active area of the detector is about 12cm x 10cm. Readout of the strips is provided through the use of VA1' ASICs mounted on custom...
Matteo Beretta
(Istituto Nazionale Fisica Nucleare (INFN) - Laboratori Nazionali di Frascati)
23/09/2010, 16:00
ASICs
Poster
We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized...
Dr
Alessandro Gabrielli
(Dipartimento di Fisica)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
An additional inner layer for the existing ATLAS pixel detector, called insertable B-layer (IBL), is under design and it will be installed by LHC-PHASE1. New front-end readout ASICs have already been fabricated and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are...
Dr
Petra Haefner
(MPI Munich)
23/09/2010, 16:00
Poster
The SemiConductor Tracker (SCT), made up from silicon micro-strip detectors is the key precision tracking device in ATLAS, one of the experiments at CERN LHC.
The completed SCT is in very good shape: 99.3% of the SCT strips are operational, noise occupancy and hit efficiency exceed the design specifications.
In the talk the current status of the SCT will be reviewed. We will report on the...
43.
Charge Sensitive Amplifier (CSA) in cold gas of Liquid Argon (LAr) Time Projection Chamber (TPC)
Herve Mathez
(Institut de Physique Nucleaire de Lyon (IPNL)-Universite Claude)
23/09/2010, 16:00
ASICs
Poster
The common channel of this 8-channel chip is made of a Low noise Charge Sensitive Amplifier (CSA) with respectively 250fF and 4MΩ feedback capacitance and resistance. The CSA is followed by a bandpass filter centred at 1µs and a buffer line driver. An ‘i2c-like’ protocol serial link allows slow control of registers, giving multiple configuration features to the circuit. The input referred...
Beat Meier
(PSI)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
The CMS pixel detector is planned to be upgraded in 2015 to a new one with a significantly reduced material budget. The new pixel system with more layers has to operate through the existing services at double the luminosity. Therefore a new readout scheme is implemented in the new pixel read out chip (ROC).
A detailed description of the ASIC modifications of the digital readout interface of...
Jennifer Merz
(RWTH Aachen University)
23/09/2010, 16:00
Power, grounding and shielding
Poster
For a new CMS tracker at SLHC cooling of the silicon sensors and their electronics is a crucial issue. An evaporative CO2 system is currently under investigation, which could provide more cooling power at a lower mass than the current mono-phase liquid system. Additionally CO2 could allow lower operating temperatures, which is beneficial for the sensor performance and lifetime.
The...
Ms
Kathrin Becker
(Bergische Universitaet Wuppertal, Germany)
23/09/2010, 16:00
Radiation tolerant components and systems
Poster
Upgrades of the LHC and the ATLAS experiment will include a new pixel detector. To operate a future pixel detector a completely new detector control system (DCS) is needed, that is embedded in the pixel electronic systems. Next to high reliabilty the requirements for the detector control system are low mass, less usage of material and cable and radiation hardness to always guarantee a save...
97.
Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs
Dr
Sandro Bonacini
(CERN)
23/09/2010, 16:00
Radiation tolerant components and systems
Poster
A new SEU-robust D-flip-flop register structure was designed in 130 nm CMOS for utilization in a rad-tolerant library. The register was tested in a heavy ion beam facility and showed a cross section lower than 1e-10 cm²/bit in the LET range (1.2 – 62.0 MeVcm²/mg) representing an improvement of 1000 times over previously studied standard library cells. No errors were observed at LETs under 30 MeVcm²/mg.
Francesco Fiori
(INFN Sezione di Pisa (INFN))
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
Experience at high luminosity hadrons collider experiments shows that tracking
information enhances the trigger rejection capabilities while retaining high efficiency for interesting physics events. The design of a tracking based trigger for Super LHC (S-LHC), the already envisaged high luminosity upgrade of the LHC collider, is an extremely challenging task, and requires the identification...
annie xiang
(Southern Methodist University)
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
This paper presents a Bit Error Rate (BER) Tester implemented in an Altera Stratix II GX signal integrity development kit. Architecture of the tester is described. Experimental and simulation results are discussed.
A parallel to serial PRBS generator and a bit/link status error detector are deployed to characterize serial data link performance. The auto-correlation pattern enables receiver...
Jia WANG
(Institut Pluridisciplinaire Hubert CURIEN,France; Northwestern Polytechnical University, China)
23/09/2010, 16:00
ASICs
Poster
This paper presents an on-chip low dropout (LDO) regulator which provides the clamping voltage in monolithic active pixel sensors (MAPS) for STAR experiment. By utilizing a buffer and a serial RC network, the regulator can achieve good stability, low power and low noise. Its output voltage is programmable by using a digital-controlled resistor. The proposed LDO regulator has been implemented...
Osamu Sasaki
(High Energy Accelerator Research Organization (KEK))
23/09/2010, 16:00
Trigger
Poster
The present muon Level-1 trigger of the ATLAS is given by dedicated detectors for the trigger; RPC and TGC chambers in barrel and endcap regions, respectively. The monitored drift tube (MDT) chambers and the CSC are used for precision measurements of muon tracks. The performance of the muon Level-1 trigger is limited by the momentum resolution of the trigger chambers. In order to improve the...
Mr
Takashi Hayakawa
(Department of Physics-Kobe University-Unknown)
23/09/2010, 16:00
Poster
In 2009 the first beam collision was occurred at LHC and the ATLAS detector has started data taking with beam collision at 7TeV since May 2010.
Thanks to the eagerest commissioning works with test pulses, cosmic rays and single beams, the Level-1 endcap muon trigger system can successfully provide trigger signals on proper timing for the ATLAS detector. The phase adjustment of the gate...
Mr
Tim Martin
(University of Birmingham, UK)
23/09/2010, 16:00
Trigger
Poster
The design of minimum bias triggers should allow for a highly efficient selection on pp-collisions, while minimising any possible bias in the event selection. In ATLAS two main minimum bias triggers have been developed using complementary technologies. A hardware based first level trigger, consisting of 32 plastic scintillators, has proven to efficienctly select pp-interactions. In particular...
Ricardo Marco Hernandez
(Instituto de Fisica Corpuscular (IFIC)-Universitat de Valencia-U)
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
A telescope for a beam test have been developed and it is described. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment.
The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test...
Mr
Sebastian Manz
(Heidelberg University)
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
Since 2007 we design and develop a ROC (read-out controller) for FAIR's data-acquisition. While our first implementation solely focused on the nXYTER, today we are also designing and implementing readout logic for the GET4 which is supposed to be part of the ToF detector and the CBM-XYTER which is supposed to be used in various other detectors like the STS or the TRD detectors. Furthermore we...
Tullio Grassi
(FNAL / Univ. of MD)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
We present an upgrade plan for the CMS HCAL front-end electronics. The HCAL upgrade is required for the increased luminosity of SLHC Phase I which is targeted for 2015. A key aspect of the HCAL upgrade is to add detector segmentation. The increased segmentation is achieved by replacing the hybrid photodiodes (HPDs) with silicon PMTs (SiPMs). We plan to instrument each fiber of the calorimeter...
Dr
Gisèle MARTIN-CHASSARD
(Laboratoire de l Accélérateur Linéaire)
23/09/2010, 16:00
ASICs
Poster
PARISROC is the front-end ASIC designed to read 16 photomultiplier (PM) tubes for neutrino experiments. It’s able to shape, discriminate, convert and readout data in an autonomous and channel-independent mode. The tests made on PARISROC1 have shown some limitations on time measurements and on hit rate capability. In order to correct these points, the digital part of PARISROC2 has been...
Mr
Christian Irmler
(HEPHY Vienna)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
A major upgrade of the KEK-B factory (Tsukuba, Japan), aiming a peak luminosity of 8 x 10^35 / (cm^2s), which is 40 times the present value, is foreseen until 2013. Consequently an upgrade of the Belle detector and in particular its Silicon Vertex Detector (SVD) is required. We will introduce the concept and prototypes of the full readout chain of the Belle II SVD. Its APV25 based front-end...
Dr
Paul Rubinov
(Fermilab)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
This report describes a system designed to simplify the use of SiPM in small scale projects, with 1 to 100 SiPMs. The system consists of 4ch digitizer boards (called TB4), and Windows software. Each TB4 contains 4 channels of electronics with gain appropriate for use with SiPMs, and four 14bit, 250MSPS digitizers. Each TB4 also has a Cockroft Walton voltage multiplier to generate the necessary...
Mr
Jonathan Emery
(CERN)
23/09/2010, 16:00
Production, testing and reliability
Poster
The reliability concerns have driven the design of the LHC BLM system from the early stage of the studies up to the present commissioning and the latest development of diagnostic tools.
To protect the system against non-conformities, new ways of automatic checking have been developed and implemented. These checks are regularly and systematically executed by the LHC operation team to insure...
Mr
Benjamin Lemouzy
(Conseil Europeen Recherche Nucl. (CERN))
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
The goal of the LHCb readout upgrade is to speed up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or similar technologies and might also need new networking protocols such as a customized, light-weight TCP or more specialised protocols. A test module is being implemented, which integrates in the existing LHCb infrastructure. It is a multiple 10-Gigabit traffic...
Mr
Robert Schnell
(HISKP, University Bonn)
23/09/2010, 16:00
Poster
This work presents an FPGA-based readout system for double-sided silicon strip sensors based on the APV25 Frontend-Chip. The system consists of an ADC-card and a digital readout board containing an FPGA. Data extraction algorithms implemented in the FPGA allow baseline and pedestal correction, hit detection and event-building. These algorithms provide an efficient data reduction tool and high...
Mr
Alan Prosser
(Fermilab)
23/09/2010, 16:00
Optoelectronics and Links
Poster
Particle physics detectors utilize readout data links requiring a complicated network of copper wires or optical fibers. These links are both massive and costly. Upgrades to such detectors may require additional bandwidth to be provisioned with limited space available to route new cables or fibers. In contrast, free-space optical interconnects will offer cableless readout, thereby resulting in...
Mr
Andrej Seljak
(Jožef Stefan institute, Ljubljana Slovenia)
23/09/2010, 16:00
ASICs
Poster
For the upgrade of the Belle detector (Belle-II) at the KEK collider, we are developing a proximity focusing ring imaging Cherenkov detector using aerogel as radiator, which will allow efficient separation of kaons from pions in the wide range of particle momenta up to 4Gev/c. One of the photon detector candidates (which has to operate in a strong magnetic field of 1.5T) is a HAPD of proximity...
Dr
Fernando Arteche
(Instituto Tecnologico de Aragon)
23/09/2010, 16:00
Power, grounding and shielding
Poster
The characterization of the noise emissions of DC-DC converters and their impact at the system level is critical to optimize the design of the detector and define rules for the integration strategy. This paper presents the effects of the circuitry impedance of the tracker power distribution network on the noise emissions of DC-DC converters. It allows to quantify the real noise emitted by the...
Dr
Andrea Salamon
(INFN Sezione di Roma Tor Vergata)
23/09/2010, 16:00
Optoelectronics and Links
Poster
We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ module.
QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps.
We implemented a complete testbench based on a commercial development card mounting an Altera Stratix IV FPGA...
Yoshinobu Unno
(KEK)
23/09/2010, 16:00
Power, grounding and shielding
Poster
A low voltage power supply was developed with a step-down piezoelectric transformer (PT), capable of supplying up to 4 A at an output voltage of 2 V, where the efficiency was estimated to be better than 80 %. The PT was 15 by 15 by 5 mm in size and composed of two layers at the primary and of 40 layers at the secondary. A new PT is manufactured with an improved process to have a reduced...
Dr
Daniel Tapia Takaki
(University of Birmingham / at CERN)
23/09/2010, 16:00
Production, testing and reliability
Poster
In the ALICE experiment, the Low-Voltage Differential Signalling (LVDS) format is used for the transmission of trigger inputs from the detectors to the Central Trigger Processor (CTP), the L0 trigger outputs from Local Trigger Units (LTU) boards back to the detectors and the BUSY inputs from the sub-detectors to the CTP. ALICE has designed a developed set-up, called the LVDS transmission...
Ms
Sylvie BLIN
(LAL Orsay - IN2P3)
23/09/2010, 16:00
ASICs
Poster
The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors.
Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs.
A multiplexed analog charge output is also available with a...
Dr
Tobias Flick
(Bergische Universitaet Wuppertal)
23/09/2010, 16:00
Optoelectronics and Links
Poster
Future high energy physics experiments will operate at energies much higher than the present ones. To read out even the innermost detectors electronics and optical components must be developed to survive the harsh conditions during the lifetime of the experiments. It has been found that for VCSEL the irradiation hardness is connected to the temperature behavior of the device and that an...
Thomas Würschig
(HISKP, Uni Bonn)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
The Micro-Vertex-Detector is the innermost detector of the PANDA experiment using silicon pixel detectors in the inner and double-sided microstrip detectors in the outer parts.
The ongoing hardware development, the implementation of the cooling system and the detector integration will be highlighted. This includes a summary of measurements with test systems, the machining of support...
Gisèle Martin-Chassard
(OMEGA, Laboratoire de l'Accélérateur Linéaire, LAL, Université Paris-Sud, CNRS/IN2P3)
23/09/2010, 16:00
ASICs
Poster
MICRO MEsh GAseous Structure (MICROMEGAS) and Gas Electron Multipliers (GEM) detectors are two candidates for the active part of a Digital Hadronic CALorimeter (DHCAL) as part of a high energy physics experiment at the International Linear Collider. Physics requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital...
Mr
Pavel Stejskal
(CERN)
23/09/2010, 16:00
Optoelectronics and Links
Poster
Optical link components will typically be exposed to intense radiation fields during operation in the SLHC inner detectors and their qualification in terms of radiation tolerance is thus required. We have created a model that describes a semiconductor laser undergoing irradiation to enable the extrapolation to full lifetime total fluences from lower fluence radiation tests. This model uses a...
Mr
Spyridon Georgakakis
(CERN)
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
High Level Synthesis takes an abstract behavioural or algorithmic description of a digital system and creates a register transfer level structure that realises the described behaviour. Various methodologies have been developed to perform such synthesis tasks. Much research has lead to the development of electronic design automation tools capable of HLS that are now being accepted by industry....
Mr
Alan Prosser
(Fermilab)
23/09/2010, 16:00
Optoelectronics and Links
Poster
This paper describes the assessment of commercially available and prototype parallel optics modules for possible use as back end components for the Versatile Link common project. The assessment covers SNAP12 transmitter and receiver modules as well as optical engine technologies in dense packaging options. Tests were performed using vendor evaluation boards (SNAP12) as well as custom...
Mr
Sergio Silva
(INESC Porto, Faculdade de Engenharia, Universidade do Porto)
23/09/2010, 16:00
Optoelectronics and Links
Poster
In an optical transceiver, the power consumption related to the operation of the laser device takes a significant parcel of the total consumed power. The reduction of it is an important issue when a large number of transceiver devices are interconnected in an optical network, such as the one that supports the data transmission in particle physics experiments. An analysis and simulation results...
Mr
Brad Weber
(Max Planck Institute For Physics - Munich)
23/09/2010, 16:00
ASICs
Poster
We present the performance of a newly developed analogue chip for readout of the ATLAS muon drift-tube (MDT) chambers, using the IBM 130 nm CMOS 8RF-DM technology. The 4-channel Amplifier-Shaper-Discriminator (ASD) chip of 2.1 * 2.1 mm2 size was designed to match the analogue performance of the presently used device in 0.5 um Agilent technology, which is now obsolete. The aim of this first...
Mr
Ringo Schmidt
(Deutsches Elektronen-Synchrotron (DESY))
23/09/2010, 16:00
Poster
The Beam Conditions and Radiation Monitoring System, BRM, is implemented in CMS to protect the detector and provide an interface to the LHC. Seven sub-systems monitor beam conditions and the radiation level on different time scales. They detect adverse beam conditions, facilitate beam tuning close to CMS, and measure the doses accumulated in different detector components. Data are taken and...
Mr
Eric Wanlin
(Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
The next generation of proton decay and neutrino experiments, the post-SuperKamiokande detectors as those that will take place in megaton size water tanks, will require very large surfaces of photodetection and a large volume of data. Even with large hemispherical photomultiplier tubes (PMT), the expected number of channels should reach hundreds of thousands. An french ANR funded R&D program...
Mr
G. Spiazzi
(Universita di Padova, Italy)
23/09/2010, 16:00
Power, grounding and shielding
Poster
This paper investigates the use of switching converters for the power supply distribution network in the ATLAS experiment when the Large Hadron Collider (LHC) will be upgraded beyond the nominal luminosity. Due to the highly hostile environment the converters must operate in, all the main aspects are considered in the investigation, from the selection of the switching converter topologies to...
Mr
Chonghan Liu
(Southern Methodist University)
23/09/2010, 16:00
Optoelectronics and Links
Poster
A number of critical active and passive components of optical links are successfully tested at 77 K or lower, demonstrating a potential to develop optical links operating inside the Liquid Argon Time Projection Chamber (LArTPC) detector cryostat. Ring oscillators, individual MOSFETs, and a 16:1 5-Gbs serializer fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS technology...
Yoichi Ikegami
(KEK)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
The main goal of this R&D program is to prove to the community that a modular silicon strip tracker concept is a reasonable design that can satisfy the required material, mechanical, electrical and thermal performance specifications throughout the SLHC period. The R&D program places considerable emphasis on design aspects that minimize the development and construction effort and cost, while...
Mr
Jan Sammet
(RWTH Aachen University)
23/09/2010, 16:00
Power, grounding and shielding
Poster
A new powering scheme is considered to be mandatory for the CMS tracker at SLHC. The baseline solution of CMS foresees the use of DC-DC converters, allowing to provide larger currents while reducing losses. An important component of most converters are inductors, which, however, tend to radiate the switching noise generated by the converter. The radiated emissions of several converters have...
Mr
Alan Prosser
(Fermilab)
23/09/2010, 16:00
Power, grounding and shielding
Poster
The upgrades of the Large Hadron Collider (LHC) introduce a significant challenge to the power distribution of the detectors. DC-DC conversion is the preferred powering scheme proposed to be integrated for the CMS tracker to deliver high input voltage levels and performing a step-down conversion nearby the detector modules. In this work, we investigate the integrity of power distribution and...
Michael King
(Vanderbilt University)
23/09/2010, 16:00
Radiation tolerant components and systems
Poster
The radiation response of a commercial 0.25 μm silicon-on-sapphire CMOS technology was characterized at the transistor and circuit levels utilizing standard or enclosed layout devices. Device-level characterization showed ΔVT of less than 170 mV and ΔILEAKAGE of less than 1 nA for nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit...
Mr
Salleh Ahmad
(LAL,Orsay - IN2P3)
23/09/2010, 16:00
ASICs
Poster
SPACIROC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). This 64 channels readout ASIC offers photon counting capability and includes a charge to time (Q-to-T) converter. The main requirement for the photon counting is to obtain a 100% trigger efficiency starting from 1/3 p.e. with a 10 ns double pulse resolution. As for the Q-to-T converter, the chip...
Dr
Timo Tick
(CERN – PH department, 1211 Geneva 23 Switzerland, On behalf of all the members of the Medipix HPD team)
23/09/2010, 16:00
Packaging and interconnects
Poster
This paper describes the design of a high-speed, single-photon counting, hybrid photon detector. The detector consists of a vacuum tube, containing a micro channel plate and 4 CMOS pixel read out chips, sealed with a transparent optical input window with a photocathode.
The described design utilizes currently available technologies, specifically the Timepix read out chips, and the Photonis...
Mr
Pablo Fernandez Carmona
(CERN)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
To reach a sufficient luminosity, the transverse beam sizes and emittances in future linear particle accelerators should be reduced to the nanometer level. Mechanical stabilization of the quadrupole magnets is of the utmost importance for this. The piezo actuators used for this purpose can also be used to make fast incremental orientation adjustments with a nanometer resolution.
The main...
Mr
Sebastien Drouet
(Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11)
23/09/2010, 16:00
ASICs
Poster
PARISROC_V2 is a complete read out chip, in AMS SiGe 0.35µm technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and its belongs to an R&D program funded by the French national agency for research (ANR) called PMm²: “Innovative Electronics for photodetectors array used in High Energy Physics and Astroparticles”. The ASIC integrates...
Michel Morel
(CERN)
23/09/2010, 16:00
Packaging and interconnects
Poster
The NA62 Giga Tracker is a low mass time tagging hybrid pixel detector operating in a particle rate of 800 MHz. It consists of three stations with a sensor size of 60 x 27 mm^2 containing 18000 pixels of the size 300 x 300 µm^2 each. The active area is connected to a matrix of 2 x 5 pixel ASICs, which time tags the arrival of the particles with a binning of 100 ps. The detector operates in...
Sophie Baron
(CERN)
23/09/2010, 16:00
Optoelectronics and Links
Poster
The Gigabit Link Interface Board (GLIB) is an evaluation platform and an easy entry point for users of high speed optical links in high energy physics experiments. Its intended use ranges from optical link evaluation in the laboratory, to control triggering and data acquisition from remote modules in beam or irradiation tests. The GLIB is a double width Advanced Mezzanine Card (AMC)...
Markus Friedl
(HEPHY Vienna)
23/09/2010, 16:00
Optoelectronics and Links
Poster
The pixel detector of the CMS experiment at the LHC is read out by analog optical links, sending the data to 9U VME Front-End Driver (FED) boards located in the electronics cavern. There are plans for the phase 1 upgrade of the pixel detector (~2015) to add one more layer, while significantly cutting down the overall material budget. At the same time, the optical data transmission will be...
Dr
Saverio Minutoli
(INFN - Genova)
23/09/2010, 16:00
Systems. Planning, installation, commissioning and running experience
Poster
The TOTEM Read-Out Card (ROC) is the main component of the T1 forward telescope front-end electronic system. It is mounted in the “Local Detector region” of the T1 detector structure between the “On Detector Region” represented by the front-end hybrids and the “Counting Room”. The ROC main objectives are to acquire tracking data and trigger information from the T1 Cathode Strip Chamber (CSC)...
Mr
Mikhail Matveev
(Rice University)
23/09/2010, 16:00
Optoelectronics and Links
Poster
The present Muon Port Card (MPC) provides sorting of incoming
Level 1 Trigger primitives and optical transmission of three best ones to the Track Finder within the Cathode Strip Chamber CSC)sub-detector at the CMS experiment at CERN.
The transmission system comprises 180 1.6Gbps links; it has been in operation since 2008. The proposed Super-LHC upgrade implies higher data volume to be...
Andrei Khomich
(Kirchhoff-Institut fuer Physik, Heidelberg University)
23/09/2010, 16:00
Trigger
Poster
The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM)consisting...
Mr
Markus Fras
(Max-Planck-Institut fuer Physik)
23/09/2010, 16:00
Programmable Logic, design tools and methods
Poster
The Triple Modular Redundancy (TMR) technology allows protection of the functionality of FPGAs against single event upsets (SEUs). Each logic block is implemented three times with a 2-out-of-3 voter at the output. Thus, the correct logical value is available even if there is an upset bit in one location. We applied TMR to the configuration code of a Virtex-II-2000 FPGA, which serves as the...
