As the LHC experiments are undergoing significant upgrades to prepare for the High Luminosity LHC run expected for 2027, trigger algorithms need to be redesigned to cope with the higher expected detector occupancy and the increased readout capabilities. Recent developments on the implementation of Neural Networks (NNs) on FPGA have opened the stage to low-latency inference, enabling highly specialized tasks to be carried out at trigger level. A muon tracking trigger algorithm is presented, combining NNs and analytic processing of time digitized signals generated on FPGA from drift tubes muon detectors. NNs are implemented on-line to univocally select signals compatible with genuine muons, thus removing the otherwise large amount of combinatorial. A fully integrated demonstrator based on CMS phase-2 upgrade front-end electronics is used as a testbed, where the trigger algorithm is fully implemented on a Xilinx Kintex Ultrascale. The algorithm and its performance will be described.
|TIPP2020 abstract resubmission?||No, this is an entirely new submission.|