The Compressed Baryonic Matter (CBM) experiment at FAIR needs a detector to measure the nucleus-nucleus collision centrality and orientation of the reaction plane. This will be obtained with the Projectile Spectator Detector (PSD), which is a sampling lead/scintillator forward hadron calorimeter.
The PSD readout system is based on ADC FPGA board (14-bit resolution and 125MHz digitization) which was originally designed for ECAL@PANDA. In order to integrate the PSD ADC board to the common CBM DAQ, a FPGA-GBT component was included into the FPGA design with a clock switching procedure to run the ADC board with the recovered GBT receive clock in order to synchronize the hardware to the common CBM DAQ time.
The development of components for digitizing waveforms reaching 1MHz readout rate per channel tested in mCBM test runs and the trigger-less readout will be discussed as well as the inclusion of the readout into the next-generation mCBM readout scheme.