Speaker
Description
A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board. The board has 22 simplex optical links to transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector electronics. The board implements 2 duplex optical links for clocks, control, and monitoring with redundancy design to improve the system reliability. Major functions of the board have been verified.
Summary (500 words)
An optical link system is being developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. A prototype-link board has been designed to evaluate the full optical links of the future Front-End Board (FEB). The prototype-link board consists of 24 lpGBT chips and 8 VTRx+ modules. Two lpGBT chips, two VTRx+ modules, and two pairs of duplex fibers constitute the control links to distribute clocks and Bunch Crossing Reset signals and control the whole FEB. These lpGBT chips and the VTRx+ modules operate in the transceiver mode. The rest 22 lpGBT chips operating in the transmitter mode, 6 VTRx+ modules with only transmitter channels in operation, and 22 simplex optical fibers form data links. The data links transmit detector data, which are emulated in FPGAs and injected through 6 FMC connectors, to the off-detector electronics. The prototype link board has been tested successfully and major functions of the board have been verified.
The prototype-link board demonstrates the redundancy design of control links. First, the clock distribution is redundant. If a downlink is broken (either the VTRx+ is out of order or the fiber is broken), the corresponding control lpGBT can use a clock from another control lpGBT as the reference clock source. Second, the distribution of BCR signals is redundant. Each control lpGBT has 16 electrical link output ports, each driving an ADC ASIC. Two electrical link output signals from two control lpGBT chips are added and multiple dropped to two ADC ASICs to deliver the BCRs signals. The addition is implemented in a Y-shape resistor network. If a downward control link is broken, its electrical link driver is set up to output a stable low and the driver from another downward control link can still drive the target ASICs. Third, the redundancy design of I2C configuration has been implemented. All ASICs used on the FEB adopt an I2C interface. Each I2C bus has dual controllers, a primary one and a secondary one. If the control link to the primary I2C controller is lost, the secondary controller can take over the bus. At last, all ASICs, including control lpGBT chips and VTRx+ modules, can be reset or power cycled. Though the failure probability of control lpGBTs is lower than the fibers and optical modules, a malfunctioning control lpGBT and VTRx+ may need a reset or a power cycle. The prototype-link board is divided into two symmetric halves called Halves A and B afterward. The control lpGBT on Half A can reset or power cycle all the ASICs, including the control lpGBT and VTRx+, on Half B, and verse versa. All the redundant designs have been verified on the proto-link board except that the BCR distribution. The redundancy design of BCR distribution has been simulated, is being verified, and will be reported in the workshop.
