Speaker
Description
The building blocks of the upgraded ATLAS Strip Tracker for HL-LHC are modules that host silicon sensors and front-end ASICs. The modules are mounted on carbon-fibre substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card on each substructure connects up to 28 differential data lines at 640 Mbit/s to lpGBT and VL+ ASICs that provide data serialisation and 10 GBit/s optical data transmission to the off-detector systems respectively. Prototype EoS cards have been designed and extensively tested using lpGBT and VL+ prototypes. The status of the electronics design and recent test results are presented.
Summary (500 words)
The silicon tracker of the ATLAS experiment will be upgraded for the upcoming High-Luminosity Upgrade of the LHC (HL-LHC). The main building blocks of the new strip tracker are modules that consist of silicon sensors and hybrid PCBs hosting the read-out ASICs. The modules are mounted on rigid carbon-fibre substructures, known as staves in the central barrel region and petals in the end-cap regions, that provide common services to all the modules. At the end of each stave or petal, a so-called End-of-Substructure (EoS) card facilitates the transfer of data, power, and control signal between the modules and the off-detector systems. The module front-end ASICs transfer data to the EoS card on 640 Mbit/s differential lines. The EoS connects up to 28 data lines to one or two lpGBT chips that provide data serialisation and uses a 10 GBit/s versatile optical link (VL+) to transmit signals to the off-detector systems. The lpGBT also recovers the LHC clock on the downlink and generates clock and control signals for the modules. To meet the tight integration requirements in the detector, several different EoS card designs are needed. We have produced prototypes of the different designs using the currently available versions of the lpGBT and VL+ ASICs. The EoS is powered by a two-stage DC-DC converter, generating both 2.5 V and 1.2 V out of the incoming 11 V, mounted on a custom-designed daughter board which will be connected to the EoS during assembly. We will here present the current status of the EoS card’s electronics design, results from extreme temperature and magnetic field tests, preliminary results from error rate tests in the presence of neutron radiation to test for susceptibility to single-event-upsets and detailed studies of the optical signal quality. We will also discuss the first results from full integration tests with the final design of the DC-DC converter, as we move towards production of the first 5% for final staves/petals. Since each EoS sits at a single-point-of-failure for an entire stave or petal side, a dedicated quality control (QC) and assurance (QA) procedure for the production has been developed. An overview of the QA and QC will also be presented.
