Speaker
Description
An exercise of implementing and testing a 3D track segment seeding engine core based on the Tiny Triplet Finder in a low-cost FPGA device is reported. The seeding engine is designed to preselect and group hits (stubs) from cylindrical detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hugh transform space for r-z view and a Tiny Triplet Finder for r-phi view to implement 3D constraints. The seeding engine is organized as a pipeline so that each hit is processed in a single clock cycle. Test results show that the seeding engine operates as expected.
Summary (500 words)
In most track segment recognition tasks, the first stage, track segment seeding (i.e., grouping the first a few detector layer hits belonging to a track) is one of the most time or silicon area resource consuming operations (not only in online trigger systems but also in offline data analysis). A track segment finding scheme called Tiny Triplet Finder featuring small FPGA resource usage was developed for Fermilab BTeV project. Today, it becomes possible to further utilize more compact FPGA resources such as multipliers (instead of purely using logic elements) to implement the Tiny Triplet Finder with even better resource usage efficiency.
On the other hand, in high luminosity detectors, segment seeding in 2D (in r-phi or r-z plane only) becomes insufficient, since the probability of finding fake segments becomes too high. To reduce fake rate, 3D segment seeding with both r-phi and r-z constraints becomes necessary. Since the Tiny Triplet Finder uses significant less resources than typical implementation methods, it enables the possibility to implement 3D track segment engines with reasonable sized FPGA. The FPGA 3D track segment seeding engines can be used in either online trigger systems or as a co-processor for offline analysis acceleration.
We have exercised implementing a 3D seeding engine core with a 10x256-cell Hugh transform space for r-z view and a 128-bin Tiny Triplet Finder for r-phi view in an Altera Cyclone 5 FPGA (5CGXFC5C6F27C7N) and tested in an evaluation module. In time domain, the seeding engine uses 225 clock cycles to process an event (BX) with 112 cycles to fetch Layer 1 and Layer 3 hits into Hugh transform space and next 112 cycles to pass the Layer 2 hits through the Hugh transform space and Tiny Triplet Finder for 3D coincidence, plus 1 cycle to reset the engine for next event. Up to 112 hits per layer are allowed for each event and a new event is allowed to connect to the previous event seamlessly. (The number of clock cycles, 225 is chosen based on 18x multiplexing in time domain in current arrangement of CMS TFP assuming core clock runs at 500 MHz).
Hits are generated in an idealized detector with diameters and lengths the same as the CMS Outer Tracker PS layers. Each engine core processes a range of detector area 10 degrees x 240 cm. Each event contains 10 good tracks (PT>2GeV/c) plus up to 102 random hits per layer which is higher than the HL-LHC operating condition. The acceptances in various stages are chosen to be as wide as possible so that the final good track acceptance is better than 99%. Under this condition, the fake hit rejection rate is still better than 80%.
The Hugh transform lookup tables and the Tiny Triplet Finder coincidence map are geometry dependent and they are specified with two ROM initiation files and a VHDL file. These files are generated automatically in simulation, which allows accurate coincidence implementation and flexibility of applying the firmware for different detectors and accommodate offsets due to misalignment.
