Conveners
Trigger
- Gregory Michiel Iles (Imperial College (GB))
Trigger
- Gregory Michiel Iles (Imperial College (GB))
The Muon-to-Central Trigger Processor Interface (MUCTPI) was completely redesigned as part of the ATLAS Level-1 trigger upgrade for Run 3 of the LHC. The new system is implemented as a single ATCA module, using three large state-of-the-art FPGAs and high-density fibre-optic modules. 208 high‑speed links receive trigger information from the muon trigger detectors, while 60 links are used to...
The throughput and processing requirements of the CMS L1 Trigger for HL-LHC require platforms with high-end FPGAs and many high speed optical links. The Ocean platform features the largest ZYNQ Ultrascale+ SoC and 72 transceivers connected to on-board optics reaching rates up to 28 Gbps. The Octopus^2 design targeted for the CMS Muon Trigger at HL-LHC features a Virtex Ultrascale+ 13P FPGA in...
The HL-LHC will start operations in 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined. Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition system. Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The hardware implementation...
The High-Luminosity LHC will put significant demands on trigger systems. To control trigger thresholds, the CMS Collaboration is designing a novel Level-1 track trigger. The Outer Tracker will use modules with pairs of sensor layers to read out hits compatible with charged particles above 2-3 GeV. The system will combine these front-end trigger primitives to reconstruct tracks, providing a...
In Run-3 beginning in 2022, the LHCb software trigger will start reconstructing events at the LHC average crossing rate of 30 MHz. Within the upgraded DAQ system, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction, in view of future runs at even higher luminosities.
One such solution is a highly-parallelized custom tracking processor...
An exercise of implementing and testing a 3D track segment seeding engine core based on the Tiny Triplet Finder in a low-cost FPGA device is reported. The seeding engine is designed to preselect and group hits (stubs) from cylindrical detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hugh transform space for r-z view and a Tiny Triplet Finder for r-phi...
