TWEPP 2021 Topical Workshop on Electronics for Particle Physics

Session

Posters Trigger

21 Sept 2021, 17:20

60. Hardware Design of the Generic Rear Transition Module for Global Trigger System of the ATLAS Phase II Upgrade

Weigang Yin (Brookhaven National Laboratory (US))

21/09/2021, 17:20

Trigger

Poster

In the ATLAS Phase-II upgrade, Global Trigger is a new subsystem that will bring event filter-like capability to the Level-0 trigger system. A common hardware platform in ATCA form factor named Global Common Module (GCM) is proposed to be configured as nodes in the Global Trigger. To mitigate the risk and simplify the GCM hardware design, a Generic Rear Transition Module (GRM) is developed....

160. Progress report on the online processing upgrade at the NA62 experiment

Matteo Turisini (Sapienza Universita e INFN, Roma I (IT))

21/09/2021, 17:20

Trigger

Poster

In 2021 the NA62 experiment at CERN is restarting data taking with upgraded instrumentation. In this framework we present the commissioning test of the new L0 trigger processor offering enhanced bandwidth, updated interconnection technology and increased logic capabilities with respect to its predecessor. We also present the latest performances of two computing-intense additional components...

183. Test poster

Alex Kluge (CERN)

21/09/2021, 17:20

Poster

Test poster description

35. The ATLAS Electron Feature Extractor Module: Design, Manufacture and Test

Saeed Taghavirad (Science and Technology Facilities Council STFC (GB))

21/09/2021, 17:20

Trigger

Poster

In Run 3, the ATLAS Level-1 Calorimeter Trigger (L1Calo) will be augmented by an Electron Feature Extractor (eFEX), which will identify isolated electron/photon and tau particles. Each eFEX module accommodates 424 signals at 11.2 Gb/s. Three generations of eFEX have been manufactured, and the design, manufacturing, and testing processes have been optimised. The firmware for the eFEX is managed...

34. The MDT Trigger Processor development for the ATLAS Level-0 Muon Trigger at HL-LHC

Guillermo Loustau De Linares (University of Massachusetts (US))

21/09/2021, 17:20

Trigger

Poster

The novel MDT Trigger Processor (MDTTP) is a fundamental component of the ATLAS Level-0 Muon trigger upgrade, designed to meet High-Luminosity LHC requirements. The MDTTP will use MDT hits to improve the momentum resolution of muon candidates provided by RPC and TGC detectors and to reduce the fake rate.
A hardware demonstrator has been developed based on the Apollo ATCA platform.
The...

155. The NA62 liquid krypton electromagnetic calorimeter fast readout implementation and data taking performances

Roberto Ammendola (INFN e Universita Roma Tor Vergata (IT))

21/09/2021, 17:20

Trigger

Poster

The NA62 experiment at the CERN SPS aims to measure the branching ratio of the very rare kaon decay $K^+\rightarrow\pi^+\nu\bar{\nu}$. The calorimeter level 0 trigger identifies clusters in the electromagnetic and hadronic calorimeters. Along with the trigger data sent to the L0 trigger processor, readout data is collected to be sent to L1 software trigger level. We present the novel...

16. Ultra-low jitter clock distribution for the trigger electronics of the ATLAS New Small Wheel experiment.

Panagiotis Gkountoumis (CERN)

21/09/2021, 17:20

Trigger

Poster

The low radiation levels on the outer rim of the New Small Wheels of the the ATLAS experiment gave the opportunity of utilizing commercial FPGAs for the trigger electronics of the sTGC detectors. The demanding requirements of the Xilinx FPGA transceivers in terms of jitter imposed the development of an ultra-low jitter clock distribution scheme. This scheme includes a custom board placed in...

171. Upgrade of the CMD-3 trigger system.

Mr Leonid Epshteyn (Budker Institute of Nuclear Physics)

21/09/2021, 17:20

Trigger

Poster

In 2017, the luminosity at the VEPP-2000 collider at the Budker Institute of Nuclear Physics SB RAS, Novosibirsk, has increased. In this regard, it was decided to upgrade the trigger system of the CMD-3 detector. For this, the development of a device called the “Final Decision Block” was started. In this paper, we consider the designing and debugging process of the created block, as well as...