Speaker
Description
A new HV-CMOS pixel chip, called MightyPix, is being developed for the Mighty Tracker, an upgrade planned for LHCb in anticipation of the HL-LHC. Extensive research is ongoing to study the tracks and occupancy at the Mighty Tracker. This data is now used to simulate MightyPix’s performance in the LHCb environment, with focus on the digital readout. First results show an efficiency of 99.7% for MightyPix for the highest hit rates expected at the Mighty Tracker, which reach 17 MHz/cm$^2$. The bottleneck was found to be the readout speed, which yielded new design ideas to further improve the digital readout.
Summary (500 words)
Part of the upgrade towards the High Luminosity LHC, is the development of a new tracker for the LHCb experiment. This tracker, called Mighty Tracker, will be hybrid, combining scintillating fibres in the outer regions and silicon sensors in the inner regions, where the hit density and radiation damage are highest. For the silicon region, a new HV-CMOS pixel chip, called MightyPix, is currently being developed. The first prototype, MightyPix1, is the first monolithic silicon sensor that has a digital periphery compatible with the LHCb online system. Various studies are ongoing to ensure that the Mighty Tracker will prove successful.
On the one side, the particle tracks and occupancy at the tracker are studied in simulations, while on the other side the general MightyPix functionality is verified by the chip designers. The studies presented here provide an interface between the two. Using the Mighty Tracker simulation data and a behavioural model of MightyPix1, representing the analogue pixel matrix, together with the synthesised digital logic, the chip’s performance within the LHCb environment is characterised. The focus lies on the digital readout of MightyPix1, to validate that the chip can handle the highest particle hit rates at the Mighty Tracker, which are expected to reach 17 MHz/cm$^2$. Studying the efficiency (which decreases with increasing occupancy) over the whole silicon region of the tracker can inform decisions on the number of readout links in different tracker areas. Looking at the behaviour of the digital readout can additionally reveal bottle necks in the design. The idea behind this verification process is to provide a simple framework on top of the Cadence tool chain, written in python, to make use of the complex work done in different areas, namely the extensive simulations of particle tracks and the design of the HV-CMOS pixel chip. The framework is constructed for an easy exchange of simulation data as well as chip model, making it possible to use it for different chips and environments.
First simulation results yield an efficiency of 99.7% for hit rates of 17 MHz/cm$^2$ (Fig. 1), showing that MightyPix1 can handle the maximum rates expected at the Mighty Tracker. Further investigations show the limiting factor being the readout time of the hits. For 17 MHz/cm$^$2 the maximum readout times lie around 7 us, while for 50 MHz/cm$^2$ they reach 190 us (Fig. 2). This is due to the much higher number of hit buffers (one for each of the 9280 pixels) compared to the column buffers (one for each of the 29 columns). Increasing the number of column buffers by a factor two means the hits can be read from the hit buffers twice as fast. For a hit rate of 50 MHz/cm$^2$ this reduces the peak readout times to 100 us (Fig. 3) and increases the efficiency of MightyPix1 from around 84% to over 96%. Although such high rates are not expected for the current Mighty Tracker design, the new readout scheme would permit installing MightyPix chips even closer to the beam pipe.
