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Description
A charge-redistribution ADC with 10-bit resolution is implemented in the TPSCo 65nm CMOS process. The design is intended for flexible on-demand monitoring of vital system signals, such as temperature, in MAPS detectors. The successive approximation principle is implemented using only two matched capacitors and a trimming DAC, while an internal clock generator and digital sequencer are used to generate control signals for stepping through the conversion phases. The clock generator has a programmable output frequency, allowing sampling rates of 50–500 kS/s. Layout area is minimized by optimizing the transistor count within the sequencer as well as careful full-custom layout.
Summary (500 words)
The measurement of environmental signals within an ASIC, such as temperature and bias currents/voltages, is vital to optimize system performance and longevity. While important, these signals do not need to be monitored continuously due to their slowly changing nature, therefore an on-demand ADC is of interest. Ideally, this ADC would also have a small footprint and require minimal conversion energy. To meet this requirement, a two-capacitor, charge-redistribution ADC with 10-bit resolution utilizing the successive approximation principle was implemented in the pixel sensor-optimized TPSCo 65nm CMOS process. A block diagram illustrating the SAQRADC is shown in Fig. 1. Capacitor C2 is either charged to Vref or discharged to ground based on the CHG/DCHG logic signals. Simultaneously, C1, which is precisely matched to C2 via a trimming DAC, is discharged to ground. The charge is then redistributed between C1 and C2 to obtain an output voltage that is compared to the input via a comparator fed by zero-input capacitance source followers. This charge redistribution process is performed k times, where k is the stage number (ranging from 1 to N, where N = 10 is the total number of bits). Since each stage requires 2k clock cycles to complete, a total of N(N+1) cycles are required per conversion. This relatively long conversion time is a consequence of the fact that the algorithm only uses two capacitors to eliminate the usual feedback DAC and simplify the control logic. Layout area is minimized by implementing the capacitors above the transistor circuitry as MOM structures on the upper metal layers while limiting signal routing to only the two bottom metal layers. Careful full-custom layout is used to minimize layout area while ensuring that all recommended DFM rules are followed. An example of the resulting constrained layout is shown in Fig. 2.
All the digital control signals for the ADC are generated by an internal sequence generator, whose functional block diagram is shown in Fig. 3. An internal clock generator with a tunable frequency ranging from 5 – 50 MHz outputs the system clock once triggered via the ADC_START input signal. This circuit is based on a ring oscillator implemented using Schmitt triggers with digitally adjustable hysteresis, thus eliminating the need for analog tuning. The clock generator feeds two walking-1 counters, one of which generates the DAC control signals and the other defines which bit is being computed. Since the number of cycles required for charge redistribution in the DAC is proportional to the bit number, the two walking-1 counters effectively work in tandem as a nested for-loop, as illustrated in the sequencer output waveforms shown in Fig. 4. Each counter, which is implemented as a twisted-ring (Johnson) counter, only requires 5 flip-flops for 10-bit counting. All combinational and sequential logic blocks are custom designed to minimize the total number of transistors; the final implementation only requires 731 transistors to generate all internal digital signals, including the system clock. The simulated characteristics of the ADC, along with the estimated layout area, are summarized in Table 1.
