Speaker
Description
Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are constantly challenged. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD (Event-Driven With Access and Reset Decoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one is a full device with analog pixel circuitry suited for full-field fluorescence imaging, and the second one contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of EDWARD alone.
Summary (500 words)
The EDWARD readout architecture [1], allows efficient readout of data from a chip with multiple data sources e.g., pixelated detectors. The architecture is distinguished by the fact that it works in a fully asynchronous manner i.e. the readout request can occur at any time and the arbitration between requests is devoid of priority [2]. These features eliminate the need to use the frame clock to snapshot the state of the matrix, which would be necessary to avoid switching between channels during a readout. This functionality of the EDWRD architecture is achieved thanks to arbitration based on a binary tree, the basic unit of which is an arbiter based on the Seitz arbiter structure [3]. Other advantage of the EDWARD architecture is automatic synchronization to an external clock provided, for example, by an acquisition module, which allows the chip to send data out using a standard communication protocol. The described architecture has been incorporated into the CTR (Configuration, Testability, Readout) platform and implemented in two different chip prototypes in 65nm CMOS technology. The platform is extremely modular and allows for easy scaling. The first prototype is a radiation detector named 3FI65P1 (Fig. 1.) suited for full-field fluorescence imaging. It is a hybrid 5mm x 5mm detector containing a 32x32 pixel matrix with a 100um pitch. The matrix is built in a modular fashion with 16 groups (4x4), each consisting of 64 pixels (8x8). It has been implemented as Analog-on-Top with digital logic placed between pixels in a group and between groups in the matrix. The main elements of the CTR platform are located in the group logic space (density ~84%), while the space between groups mainly contains part of the arbitration tree between groups (density ~2%) and the shared bus. All groups are connected to the shared 14-bit digital data bus, on which the address of the pixel being read out is sent, and 1 analog line, on which the analog value of the peak from the front-end peak detector is sent. The digital data is serialized and sent off-chip. Serialization is performed based on externally supplied clock with a designed frequency of 250MHz. The chip has a built-in clock divider by 14, which acts as the serializer frame clock and determines the time intervals for channel access to shared resources. This gives a maximum pixel data readout rate of 17.86MHz. The divided clock can alternatively be provided from an external source. Such a clock with a variable duty cycle will be used to observe its impact on build-in asynchronous-to-synchronous synchronization. The second prototype is based on the skeleton of the first, maintaining its dimensions. In this prototype analog front-end circuitry is replaced by digital logic (Fig. 2.) containing pulse generator with Poisson-exponential distribution [4]. This structure will allow even better study of the temporal properties of the EDWARD architecture – timing resolution, latency, maximum acceptable rate, and the signal integrity of the received data thanks to the ability to programmatically change the rate at which readout requests are generated.
