25–29 May 2026
Chulalongkorn University
Asia/Bangkok timezone

Real-time 40 MHz Track Reconstruction: The Readout and Processing Chain of the CMS Outer Tracker for HL-LHC

27 May 2026, 16:51
18m
Chulalongkorn University

Chulalongkorn University

Oral Presentation Track 2 - Online and real-time computing Track 2 - Online and real-time computing

Speaker

Marco Riggirello (Scuola Normale Superiore & INFN Pisa (IT))

Description

The High Luminosity LHC (HL-LHC) presents an unprecedented computing challenge, characterized by a pile-up of up to 200 interactions per bunch crossing and extreme data rates. To cope with these conditions, the CMS experiment is replacing its tracking system with a novel Outer Tracker capable of contributing to the Level-1 (L1) Trigger. This upgrade introduces a paradigm shift in data processing, moving high-momentum particle selection to the detector front-end to enable real-time tracking at 40 MHz.

This contribution presents the comprehensive readout and reconstruction architecture of the CMS Outer Tracker. We detail the "pT-module" concept, which utilizes correlation logic between closely spaced sensor layers to perform on-detector data reduction, rejecting hits from low-momentum tracks and reducing the data volume by an order of magnitude. We describe the resulting dual-stream data path: a high-bandwidth, continuous 40 MHz stream of "stubs" utilized for track finding, and a standard triggered readout stream where full event data is extracted from front-end buffers only upon Level-1 acceptance.

Special focus is placed on the downstream real-time reconstruction chain for the 40 MHz stream. We discuss the back-end processing performed by the Data, Trigger, and Control (DTC) boards and the subsequent Track Finding system based on the "Tracklet" algorithm. We present the implementation of this algorithm on high-performance FPGAs (Apollo boards), featuring a massive pipelined architecture of memory and processing modules designed to execute track seeding, projection, matching, and fitting within a strictly bounded latency of 4 µs. Finally, we report on the status of the firmware development, validation via software emulation, and integration tests with detector prototypes.

Author

Marco Riggirello (Scuola Normale Superiore & INFN Pisa (IT))

Presentation materials

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