25–29 May 2026
Chulalongkorn University
Asia/Bangkok timezone

Memory Layouts in the ALICE Track Reconstruction

27 May 2026, 13:45
18m
Chulalongkorn University

Chulalongkorn University

Oral Presentation Track 3 - Offline data processing Track 3 - Offline data processing

Speaker

Dr Oliver Gregor Rietmann (CERN)

Description

In high performance computing, we strive for algorithms on large arrays to be as performant as possible. However, the performance of such an algorithm is also affected by the memory layout of these arrays. The most natural memory layout is Array-of-Structures (AoS), which performs well for strided access patterns and for large classes. On the other hand, Structures-of-Array (AoS) allows for efficient vectorization upon sequential access.

Switching between different memory layouts usually requires significant changes to the surrounding code. Thus, as part of CERN’s “Next Generation Triggers” project, we have implemented two lightweight C++ libraries to abstract the memory layout from the algorithms operating on it. The first approach uses C++17 template metaprogramming while the second approach uses “reflection”, a new C++26 metaprogramming feature.

The goal of both approaches is to incur zero runtime overhead. Thus, we present benchmarks comparing these approaches to hard-coded memory layouts. Moreover, we use the second approach to show the impact of memory layouts on the performance of the ALICE O2 TPC track reconstruction on CPU and GPU.

Authors

Jolly Chen (CERN & University of Twente (NL)) Dr Oliver Gregor Rietmann (CERN)

Presentation materials

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