Conveners
ASICs: A1a
- Marcus Julian French (STFC - Science & Technology Facilities Council (GB))
ASICs: A1b
- Marcus Julian French (STFC - Science & Technology Facilities Council (GB))
ASICs: A2
- Christophe De La Taille (Inst. Nat. Phys. Nucl. & Particules (FR))
ASICs: B5a
- Luciano Musa (CERN)
ASICs: B5b
- Luciano Musa (CERN)
ASICs: B6
- Marcus Julian French (STFC - Science & Technology Facilities Council (GB))
Jakub Moron
(AGH University of Science and Technology (PL))
24/09/2013, 09:50
Oral
The design and preliminary measurements results of 10-bit Successive Approximation Register (SAR) Analog to Digital (ADC) converter are presented. The prototype of the SAR ADC was designed and fabricated in 130 nm IBM technology. Preliminary measurements show that the ASIC is functional and the obtained ENOB (effective number of bits) is of about 9.2 bits. Power consumption of the ADC is...
Jorgen Christiansen
(CERN)
24/09/2013, 10:15
Oral
The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than +/- 0.9 LSB and...
Miroslav Havranek
(Universitaet Bonn (DE))
24/09/2013, 11:10
Oral
Upgrade of luminosity of the LHC (HL-LHC) imposes severe constraints on detector tracking systems in terms of radiation hardness and ability to cope with high hit rates. One possible way of keeping track with increasing luminosity is usage of more advanced technologies. Ultra deep sub-micron CMOS technology allows design of complex and high speed electronics with high integration density. In...
Daniele Felici
(Universita e INFN Roma Tor Vergata (IT))
24/09/2013, 11:35
Oral
The availability of a sub 1-W SerDes for future LHC read-out systems is of paramount importance. This work relates to the design of two alternative architectures for the critical serializer block within a SerDes with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Two alternative architectures are implemented using a commercial 65nm...
Matteo Mario Beretta
(Istituto Nazionale Fisica Nucleare (IT))
24/09/2013, 12:00
Oral
The AMchip is a VLSI device that implements the associative memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of...
Frederic Morel
(IPHC/CNRS/IN2P3)
24/09/2013, 14:50
ASICs
Oral
A detector, equipped with 50 um thin CMOS Pixel Sensors (CPS), is being designed for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at LHC. Two CPS flavours, MISTRAL and ASTRAL, are being developed at IPHC aiming to meet the requirements of the ITS upgrade. The first is derived from the MIMOSA28 sensor designed for the STAR-PXL detector. The second integrates a...
Pierpaolo Valerio
(CERN)
24/09/2013, 15:15
Oral
A prototype hybrid pixel detector ASIC whose design is tuned to the requirements of a vertex detector for CLIC is described and first electrical measurements presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 x 64 square pixels each measuring 25 um on the side. The main features include simultaneous 4-bit measurement of...
Massimiliano De Gaspari
(CERN)
24/09/2013, 15:40
Oral
This front-end contains a single-ended preamplifier with a structure for leakage current compensation, suitable to both signal polarities. Preamplifier and discriminator are required to be fast, to allow a Time-of-Arrival measurement with a resolution of 1.56ns. Time-Over-Threshold (TOT) is also measured; the monotonicity of TOT with respect to the input charge is greatly improved as compared...
Walter Snoeys
(CERN)
24/09/2013, 16:05
Oral
ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging Sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials.
Several prototypes have already been designed,...
Davide Braga
(STFC - Science & Technology Facilities Council (GB))
26/09/2013, 09:50
Oral
The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip Tracker. The 254-channel, 130nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-PT track candidates. The chip was manufactured in January...
Dominik Wladyslaw Przyborowski
(AGH University of Science and Technology (PL))
26/09/2013, 10:15
Oral
The design and measurements of front--end electronics for straw tubes tracker (STT) at PANDA experiment are presented. The challenges for front--end electronics are discussed and the proposed architecture comprising switched gain preamplifier, pole--zero cancellation circuit (PZC), variable peaking time shaper, ion tail cancellation circuit (TC) and baseline holder (BLH) is described. The...
Michael Krieger
(University of Heidelberg)
26/09/2013, 11:10
Oral
For the readout of the transition radiation detectors of the upcoming CBM experiment at FAIR, a self-triggered multi-channel mixed signal ASIC for signal amplification, digitization, and processing is under development.
The SPADIC 1.0 chip has 32 channels, each composed of a charge sensitive amplifier, a 9 bit pipelined ADC continuously running at 25 MHz sampling rate and a programmable...
Jessica Metcalfe
(Brookhaven National Laboratory (US))
26/09/2013, 11:35
Oral
Measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130 nm CMOS and fabricated in spring 2012 are presented. The 64-channel ASIC features a novel design for use with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode including sub-threshold neighbors and first channel hit...
Gary Drake
(Argonne National Laboratory)
26/09/2013, 12:00
Oral
We present results on a new version of the QIE (Charge Integrating Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital...
Herve Marie Xavier Grabas
(CEA/IRFU,Centre d'etude de Saclay Gif-sur-Yvette (FR))
26/09/2013, 15:15
Oral
SamPic0 is a Time and Waveform to Digital Converter (TWDC) multichannel chip. Each of its 16 channels associates a DLL-based TDC providing a raw time with an ultra-fast analogue memory allowing fine timing extraction as well as other parameters of the pulse. Each channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After...
Nathalie Seguin-Moreau
(U)
26/09/2013, 15:40
Oral
Imaging calorimetry at the International Linear Collider requires highly granular and innovative detectors. Technological prototypes have been built and tested under the CALICE collaboration framework and FP6 EUDET, FP7 AIDA EU programs. These prototypes are readout by multi-channel chips named SKIROC2, SPIROC2 and HARDROC2, designed in SiGe 350 nm technology by the IN2P3 OMEGA group.
In...
Julien Fleury
(Weeroc)
26/09/2013, 16:05
ASICs
Oral
Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out.
Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement.
Citiroc is a 32-channel front-end ASIC designed to readout silicon...
