Conveners
Second Poster Session
- Mitchell Franck Newcomer (University of Pennsylvania (US))
Ivo Polak
(Acad. of Sciences of the Czech Rep. (CZ))
24/09/2014, 16:45
Power
Poster
The gain of SiPMs depends both on bias voltage and on temperature. We can compensate the temperature variation by regulating the bias voltage. We have developed and built an adaptive bias voltage regulator and performed tests in a climate chamber at CERN. Over a temperature range 1 โ 40 degrees C we have tested the performance of the bias voltage regulator with five SiPMs / MPPCs from three...
Andrea Biagioni
(INFN Rome Section)
24/09/2014, 16:46
Opto
Poster
In this paper we describe the latest generation of APEnet+ network interface card.
This new APEnet+ generation delivers a point-to-point, low-latency, 3D-torus NIC integrated in a PCIe Gen3 board based on a state-of-the-art, 28nm Altera Stratix V FPGA.
The NIC features a network architecture designed following the Remote DMA paradigm and tailored to tightly bind the computing power of modern...
Eduard Atkin
(NRNU MEPHI)
24/09/2014, 16:47
ASICs
Poster
A new approach to design of amplification blocks (such as preamps, shapers) is described. The generalized block diagram and analytic expressions for its transfer function are presented. The particular cases of this structure are classical schemes, using either the voltage or current feedback, but not limited by them.
The discussed formulas can be useful for the design of a whole range of...
Philipp Schwegler
(Max-Planck-Institut fuer Physik (Werner-Heisenberg-Institut) (D)
24/09/2014, 16:49
Systems
Poster
We report on the high-rate optimisation of a new Amplifier/Shaper/Discriminator (ASD) chip for the ATLAS Monitored Drift Tube (MDT) chambers, which have to sustain an unprecedented radiation background during LHC operation. The design of a new ASD chip is inevitable to provide enough chips for future upgrades of the MDT chamber front-end electronics and desirable to optimise the shaping...
Dr
Christophe FLOUZAT
(CEA Centre de Saclay)
24/09/2014, 16:50
ASICs
Poster
In the framework of the ALICE experiment upgrade at HL-LHC, a new tracking detector, the Muon Forward Tracker, is foreseen. To fulfill detector requirements, CMOS Monolithic Active Pixel Sensor (MAPS) technology was chosen thanks to interesting performances and properties in terms of readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This...
Matteo Di Cosmo
(Ministere des affaires etrangeres et europeennes (FR))
24/09/2014, 16:53
Systems
Poster
The MicroTCA and AdvancedTCA industry standards are candidate modular electronics platforms for the upgrade of the current generation of high energy physics experiments at CERN. The PH-ESE group at CERN launched an xTCA evaluation project with the aim of performing technical evaluations and providing support for commercially available components. Over the past years, different equipment from...
Dr
Dong Wang
(Central China Normal University)
24/09/2014, 16:54
Systems
Poster
The ALICE PHOS collaboration is carrying out a major upgrade of its readout electronics for the RUN 2 of LHC (2015-2017). The upgrade mainly includes three aspects: 1) The increase of the event readout rate; 2) The improvement of the communication stability of the interface between Front-end electronic boards and readout concentrators; 3)The compatibility to the upgraded ALICE Trigger system...
Mr
Robert Schnell
(Justus-Liebig-Universitaet Giessen (DE))
24/09/2014, 16:55
Systems
Poster
The PANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons on stationary targets. The Micro-Vertex-Detector (MVD) as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors.
Developments for the readout of the strip detectors,...
Developments for the readout of the strip detectors,...
Luigi Gaioni
(Universita e INFN (IT))
24/09/2014, 16:57
ASICs
Poster
Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed,...
David Calvo
(IFIC)
24/09/2014, 16:58
Logic
Poster
Thirty-one high-resolution time-interval measuring channels have been implemented in Field-Programmable Gate Arrays for the KM3NeT high energy neutrino telescope. Time to digital Architectures with low resources occupancy are desirable allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The required resolution to measure both,...
Joonas Petteri Talvitie
(Lappeenranta Univ. of Technology (FI))
24/09/2014, 16:59
Power
Poster
Developed for use with triple GEM detectors; the GEM Electronics Board (GEB) forms a crucial part of the electronics readout system being developed as part of the CMS muon upgrade. The objective of the GEB is three-fold; to provide stable powering and ground for VFAT3 front ends, to enable high speed communication between 24 VFAT3 front ends and an Optohybrid, and to shield the GEM detector...
Gabriel Pares
(C)
24/09/2014, 17:00
Packaging
Poster
Low mass pixel modules are developed for reducing radiation length in CERN LHC atlas system upgrade consisting of a silicon sensor flip-chipped with micro-bumps to a FEI4 read-out integrated chip. Thinning the FEI4 chips to 100 ยตm results in increasing chip bow leading to co-planarity issues during flip-chip reflow process. We demonstrate that chip deformation can be dynamically compensated...
Katharina Fein
(DESY)
24/09/2014, 17:01
Systems
Poster
MicroTCA.4 is a novel electronic standard derived from the Telecommunication Computing Architecture (TCA) and rapidly evolved to become a viable standard for demanding applications in large-scale research facilities of the high-energy physics and photon science community. DESY has taken on a coordinating role in the further development of MicroTCA.4 components as well as the further...
Pedro Vicente Leitao
(CERN)
24/09/2014, 17:02
Radiation
Poster
This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements bidirectional 4.8 Gb/s links between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional tests of the GBTX and to evaluate its performance. Total Ionizing Dose and Single-Event...
Jose Luis Sirvent Blasco
(University of Barcelona (ES))
24/09/2014, 17:03
Logic
Poster
A secondary particle shower acquisition system is under design for the new CERN wire scanner-based beam profile monitors. In these systems a thin wire passes through a circulating beam and the resulting secondary particles are detected to reconstruct the beam profile. It is proposed that the new acquisition system be based on a polycrystalline diamond detector (pCVD). The accompanying...
Erdem Motuk
(University College London)
24/09/2014, 17:04
Systems
Poster
The firmware structure and system integration of the final Clock and Control (CC) hardware for the EuXFEL 2D mega-pixel detectors are presented. The hardware was developed as a combination of an AMC board and a custom RTM that would work in a MTCA.4 crate. The firmware consists of a number of modules interconnected around a bus/register system that communicates to the control system over PCIe....
Prof.
Jinghong Chen
(University of Houston, Texas)
24/09/2014, 17:05
ASICs
Poster
We present a new charge-compensation (CC) scheme to mitigate single-event-transient effect in designing a phase-locked loop. The CC method significantly reduces SET-induced voltage perturbation at the oscillator control node as well as a faster recovery. It is triggered only when SET strikes occurs and thus does not affect normal PLL dynamics. The PLL achieves a 12.5MHz to 500MHz tuning range...
Robert Stringer
(University of Kansas (US))
24/09/2014, 17:06
Systems
Poster
The Phase I Upgrade to the CMS Pixel Detector at the LHC features a new 400 Mb/s digital readout system. This new system utilizes upgraded custom ASICs, PSI46dig Read Out Chips (ROC) and Token Bit Manager (TBM08/09) for data packaging, new optical links, and changes to the Front End Drivers (FEDs). We will be presenting the new architecture of the full readout chain, the new schema for data...
Lluรญs Freixas Coromina
(C)
24/09/2014, 17:07
ASICs
Poster
An application specific integrated circuit (ASIC) has been developed for level 1 trigger decisions in Cherenkov Telescope cameras. The ASIC comprises 7 input differential analogue channels and 2 output digital differential channels. Analogue inputs are provided by the previous trigger stage implemented in the so-called L0 ASIC. The L1 ASIC computes the analogue sum of three configurable sets...
Agnieszka Anna Zagozdzinska
(Warsaw University of Technology (PL))
24/09/2014, 17:08
Systems
Poster
The Beam Radiation Instrumentation and Luminosity Project of the CMS experiment, consists of several beam monitoring systems. One system, the upgraded Fast Beams Condition Monitor, is based on 24 single crystal CVD diamonds with a double-pad sensor metallization and a custom designed readout. Signals for real time monitoring are transmitted to the counting room, where they are received and...
Stephen Goadhouse
(University of Virginia (US))
24/09/2014, 17:10
Systems
Poster
In the CMS Hadron Calorimeter, the Clock Control Module distributes the system clock to the readout modules and supports control and monitoring of the front-end electronics. This year an upgrade prototype, called ngCCM, has been built and used for a beam-test of the upgraded Forward HCAL. The ngCCM uses a 4.8 Gbps GBT-like optical link to the counting room along with a redundant mechanism in...
Tao Zhang
(SMU)
24/09/2014, 17:11
Packaging
Poster
Thermal analysis has been essential in designing reliable IC. This becomes even more critical when multiple thin dies are stacked together to form a 3D integration. This paper presents our latest work on thermal modeling, analysis, and simulations on the prototype Vertical Integrated PRAM (proto-VIPRAM2D) chip. We proposed a sub-circuit-block level thermal simulation approach using Fourier...
Prof.
Jinghong Chen
(University Of Houston, Texas)
24/09/2014, 17:12
ASICs
Poster
This paper presents a LC-VCO PLL designed in 0.13ฮผm CMOS technology for multi-data rate serial link applications. The PLL covers a 5.6GHz to 13.4GHz tuning range by using two LC-VCO cores while remaining locked from -40ยฐC to 85ยฐC. At 25ยฐC, the PLL has a RMS random jitter (RJrms) of 0.37pS at 11.44GHz. The integrated jitter is less than 0.7pS. The PLL consumes 50.88mW of power from a 1.2V...
Mr
Juan Carlos Allica
(CERN)
24/09/2014, 17:14
Logic
Poster
At the CERN PS complex, precise fast intensity measurements are very important in order to optimize the transfer efficiencies between the different accelerators. Over the last two years a complete renovation has been ongoing, where the old electronics, based on analogue integrators, have been replaced by a fully digital system enclosed in a single VME based card.This new system called TRIC...
Tiankuan Liu
(Southern Methodist University)
24/09/2014, 17:15
Logic
Poster
We present a remote FPGA-configuration method based on JTAG extension over optical fibers. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or software development. The method combines the advantages of the slow remote JTAG configuration and the fast local flash memory configuration. We have verified that we can...
Tiankuan Liu
(Southern Methodist University)
24/09/2014, 17:16
Radiation
Poster
A prototype Liquid-argon Trigger Digitizer Board (LTDB), called LTDB Demonstrator, has been proposed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog/Digital converters and four FPGAs with embedded multi-gigabit-transceivers on each Demonstrator need high quality clocks. A clock distribution system based on commercial...
Evgeny Malankin
(NRNU MEPhI)
24/09/2014, 17:18
ASICs
Poster
A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power budget of 10mW per channel, area efficient 1.2 mW at 50 Msps 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow),...
Christian Torgersen
(University of Bergen (NO))
24/09/2014, 17:19
Trigger
Poster
A new readout control unit for the ALICE TPC in Run-2 - the RCU2 - has been designed in order to increase data throughput and radiation tolerance. Since the TTCrx ASIC project is disbanded, new ways to recover clock and data was implemented and tested. Two methods have been applied, one using the internal fabric resources of the SmartFusion2 FPGA and the other using a commercial component, the...
Per Olov Joakim Gradin
(Uppsala University (SE))
24/09/2014, 17:20
Trigger
Poster
The LHC plans to increase the design instantaneous luminosity by a factor of five.
The ATLAS experiment will upgrade its trigger and DAQ systems to preserve the acceptance
for electro-weak processes without increasing thresholds on the transverse momenta of physics objects.
The new scheme includes additional hardware to decouple a short latency system
from a longer latency one using the...
Fatah Rarbi
(IN2P3 / LPSC Grenoble)
24/09/2014, 17:22
ASICs
Poster
The PEALL chip is a Power Efficient And Low Latency successive approximation register (SAR) ADC candidate designed for the upgrade of the ATLAS experiment at the CERN LHC. The full functionality of the converter is especially achieved by an embedded high-speed clock frequency conversion generated by the ADC itself. The design and test results of the PEALL chip implemented in a commercial...
Manoel Barros Marin
(CERN)
24/09/2014, 17:23
Logic
Poster
Initiated in 2009 to emulate the GBTx serial link and test the first GBTx prototypes, the GBT-FPGA project is now a full library, targeting FPGAs from ALTERA and XILINX, allowing the implementation of one or several GBT links of 2 different types: โStandardโ or โLatency-Optimizedโ. The first major version of this IP Core was released in April 2014. This paper presents the various flavours of...
Marcos Vinicius Silva Oliveira
(Juiz de Fora Federal University (BR))
24/09/2014, 17:24
Trigger
Poster
For run 2 of the LHC, the ATLAS Level-1 trigger system will include
topological information on trigger objects in order to cope with the
increased trigger rates. The existing Muon-to-Central-Trigger-Processor interface (MUCTPI) has been modified in order to provide
coarse-grained topological information on muon candidates. A MUCTPI-to-Level-1-Topological-Processor interface (MuCTPiToTopo)...
Daniel Magalotti
(Universita e INFN (IT))
24/09/2014, 17:25
Trigger
Poster
The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions.
To extract in the required latency the track information a dedicated hardware has to be used. We propose a...
Mieczyslaw Maria Dabrowski
(Warsaw University of Technology (PL))
24/09/2014, 17:26
ASICs
Poster
Intended for implementation within the VFAT3 ASIC; the VFAT3-Comm-Port offers a single port for clock, synchronization, fast and slow control commands as well as data and slow control readout. The paper initially describes the core design which could be offered for use as an IP block in other projects. It also discusses an encoding technique which provides unique comma characters and increases...
Tetsuichi Kishishita
(University of Bonn)
24/09/2014, 17:28
ASICs
Poster
We present the recent development of the depleted Monolithic Active Pixel Sensors, implemented with an L-Foundary 150 nm process. Unlike in the case of standard MAPS technologies, this process provides a high-resistive substrate that enables large signal and fast charge collection by drift in a 50 um โ 100 um thick depleted layer, and the use of PMOS and NMOS transistors in the pixel cell...
Magnus Hansen
(CERN)
24/09/2014, 17:29
Systems
Poster
The High Luminosity LHC (HL-LHC) will provide unprecedented instantaneous and integrated luminosity. The CMS electromagnetic calorimeter (ECAL) will face a challenging environment at the HL-LHC: higher event pileup, higher radiation levels for the crystals and photodetectors, and a higher rate of anomalous signals from the APDs. To mitigate these challenges and maintain the excellent physics...
Dr
Jun Hu
(Institute of High Energy Physics, Chinese Academy of Sciences(IHEP,CAS))
24/09/2014, 17:30
Systems
Poster
The underground dark matter experiment in IHEP is direct detection of dark matter that using CsI(Na) as detector material, and rare nuclear recoil events of dark matter particles scattering on target material will be detected by photo-multiplier tubes (PMTs). This paper describes the electronics system structure we chosen for this detector; emphatically focus on the design of main modules that...
55.
Design and Testing of Combined GEM+CSC Trigger Algorithm Firmware for the CMS Muon Endcap System
Aysen Tatarinov
(Texas A & M University (US))
24/09/2014, 17:31
Logic
Poster
With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require more complex trigger algorithms to handle the increased data rate while maintaining high data collection efficiency. Higher performance trigger electronics have already been deployed in the front-end, and advanced trigger logic is under development to take advantage of the capabilities in the...
Vagelis Gkougkousis
(Universite de Paris-Sud 11 (FR))
24/09/2014, 17:32
ASICs
Poster
Innovative edgeless planar pixel sensors for the High Luminosity LHC upgrade are under production. Through 3D TCAD simulation of the production process and electric field at the inside of the detector, combined with SiMS measurements, a calibration and complete insight of the new structures is achieved. Comparison between simulated data and experimental measurements allow a calibration of the...
Mr
Sergey Katunin
(PNPI St Petersberg)
24/09/2014, 17:33
Systems
Poster
Sound velocity measurements can simultaneously determine gas composition and flow. We have developed ultrasonic analyzers with custom microcontroller-based electronics, currently used in the ATLAS detector control system, with numerous applications.
Three instruments monitor C3F8 and CO2 coolant leak rates into the nitrogen envelopes of the ATLAS silicon microstrip and pixel detectors. Two...
Tiehui Ted Liu
(Fermi National Accelerator Lab. (US))
24/09/2014, 17:34
Trigger
Poster
The challenge of the Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project is to increase pattern density through aggressive Vertical Integration. Our first step is to implement in conventional VLSI building blocks that can be used in 3D stacking. We are reporting on the first successful implementation of a conventional 2D demonstrator of the VIPRAM chip...
Jasmin Fragnaud
(Centre National de la Recherche Scientifique (FR))
24/09/2014, 17:35
Systems
Poster
The trigger readout electronics of the ATLAS LAr Calorimeters will be improved for the Phase-I luminosity upgrade of the LHC to enhance the trigger feature extraction. Signals with higher spatial granularity will be digitized and processed by newly developed front-end and back-end components. In order to evaluate technical and performance aspects, a demonstrator system is being set up which...
Alessandro Lonardo
(Universita e INFN, Roma I (IT))
24/09/2014, 17:55
Trigger
Poster
NaNet is a FPGA-BASED PCIe Network Interface Card with GPUDirect capability featuring a configurable set of channels: standard 1/10GbE and custom 34Gbps APElink and 2.5Gbps optical with deterministic latency KM3link.
GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing.
We will...
