Speaker
Description
The planned upgrade of the LHCb detector is designed to achieve 40 MHz readout (the maximum bunch crossing rate), allowing the experiment to collect 5fb^-1 of data per year. As part of this upgrade the tracking subsystem in front of the dipole magnet will be replaced by the Upstream Tracker (UT). Data from the UT will be critical to the LHCb software trigger, allowing more rapid and reliable extrapolation of tracks from the Vertex Locator to the Downstream Tracker. In addition to rapid readout, the UT will feature improved granularity to accommodate increased occupancy.
The detector consists of 4 planes with a total area of approximately 8.5 m^2, composed of single sided silicon strip sensors. The sensors are integrated with the dedicated front-end electronics into modules assembled in a double-sided fashion on vertical structures called staves, providing mechanical support and cooling. The innermost sensors have a circular cut-out at one edge to increase the acceptance near the beam pipe, and most of the sensors feature embedded pitch-adapters to match the sensor output pitch and the front-end electronics input pitch. The dedicated front-end ASIC (SALT) provides digitization with a built-in 6-bit ADC, common mode subtraction, and zero suppression and data processing and formatting. All components of the detector are designed to maintain performance through an integrated luminosity of 50 fb^-1.
The detector will commence operation together with the rest of the upgraded LHCb experiment after the LHC LS2 shutdown, currently scheduled to end in 2020. An overview of the UT design will be given and details of the performance of prototype sensors, electronics, and mechanical components, as well as the envisaged electronics system design and readout architecture, will be presented.
