Sep 25 – 29, 2006
Valencia, Spain
Europe/Zurich timezone

Recent developments on th ALICE central Trigger processor

Sep 27, 2006, 11:20 AM
Valencia, Spain

Valencia, Spain

IFIC – Instituto de Fisica Corpuscular Edificio Institutos de Investgación Apartado de Correos 22085 E-46071 València SPAIN


Orlando Villalobos Baillie (University of Birmingham)


The ALICE Central Trigger Processor is designed to process signals from triggering detectors and send appropriate trigger signals and data to participating detectors. The ALICE system allows dynamic partitioning of the detector, past-future protection appropriate to each detector's electronics, and a number of different monitoring and diagnostic functions. The system has now been built, and consists of 6 6U VME boards with logic implemented on ALTERA CYCLONE FPGAs. In this paper the characteristics of the system are described and its performance in tests described. Tests related to the system integration will also be presented.


The primary purpose of the ALICE experiment is to study
heavy ion
collisions. Under these conditions the luminosity will be far
than in proton proton collisions (L = 10^27 cm-2 s-1 in Pb-Pb
collisions). The ALICE experiment programme will include
runs with
several different ion species, and also both proton nucleus
and pp
runs. Note that several of the detector subsystems would
not be able
to follow the high luminosity pp running conditions, and for
reason ALICE receives a lower pp luminosity of around
10^30 cm-2

The ALICE trigger system operates with interaction rates
about 8 kHz and 300kHz. It must provide a number of
services. There are three different trigger levels (L0, L1 and
with latencies from 1.2 microseconds to 88 microseconds.
The system
allows dynamic partitioning in order to make optimum use of
readout. The system has a flexible provision for past-future
protection. The system also allows for special provision for
priority ("rare") triggers. These features have been
described in
detail at previous workshops.

The trigger system was built in 2005 and has been tested in
considerable detail. There are six different types of 6U VME
in the CTP system, and two further boards required for fan-
in and
trigger distribution. Apart from the fan-in board, which is
these share a common architecture base on ALTERA
These FPGAs are loaded from a flash memory, which is
loaded via VME.
This feature makes it easy to distribute firmware upgrades,
as has
been done in the case of the Local Trigger Unit (LTU), where
are in use at ALICE institutes around the world.

The three trigger levels involve several signal types from the
The L0 trigger is sent as an LVDS signal; the L1 signal is
sent on
channel A of the TTC system; trigger data associated with
level 1 is
sent as a message on channel B of the TTC system; the L2
trigger is
sent as a message on the TTC system after a delay,
currently 88
microseconds, to allow for the longest required past-future
protection interval. Additional possibilities exist in the case of
calibration triggers. Examples of these sequences from CTP
measurements will be shown, and in addition a
measurement of the CTP
internal decision time.

In order to control the CTP an extensive software
development was
required. The ALICE CTP is in the experiment cavern, and
is inaccessible during running time. For this reason particular
attention has been paid to monitoring and debugging
Configuration of the system is possible in a two-tier system,
experts able to change all parameters while normal users
already prepared configurations from a database. Trigger
data is
sent to dedicated monitoring processors, to the data
acquisition and
to the detector control system. A protocol based on SMI++ is
developed to make an interface to the experiment control
(ECS). All these systems will be reviewed. A more detailed
description of the CTP software is the subject of a separate
contribution to this conference.

Primary author

Orlando Villalobos Baillie (University of Birmingham)

Presentation materials